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FMC ADC 100M 14b 4cha - Gateware
Commit e5e8da78 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: restructured adc_serdes module

parent cb6feb94
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Showing with 7 additions and 11 deletions
hdl/adc/rtl/Manifest.py
View file @ e5e8da78
......@@ -9,4 +9,5 @@ files = [
"offset_gain_s.vhd",
"var_sat_s.vhd"]
modules = { "local" : ["timetag_core/rtl"] }
modules = { "local" : [ "timetag_core/rtl",
"../../ip_cores/adc-serdes-core" ] }
hdl/spec/syn/Manifest.py
View file @ e5e8da78
......@@ -8,9 +8,7 @@ syn_top = "spec_top_fmc_adc_100Ms"
syn_project = "spec_fmc_adc_100Ms.xise"
syn_tool = "ise"
files = [
"../spec_top_fmc_adc_100Ms.ucf",
"../../ip_cores/adc_serdes.vhd"]
files = ["../spec_top_fmc_adc_100Ms.ucf"]
modules = { "local" : ["../rtl",
"../../adc/rtl"],
......
hdl/spec/testbench/top/Manifest.py
View file @ e5e8da78
......@@ -8,8 +8,7 @@ include_dirs=["../include","gn4124_bfm", "ddr3"]
files = [
"main.sv",
"ddr3/ddr3.v",
"../../../ip_cores/adc_serdes.vhd"]
"ddr3/ddr3.v"]
modules = { "local" : [ "gn4124_bfm",
"../../rtl",
......
hdl/svec/sim/testbench/Manifest.py
View file @ e5e8da78
......@@ -5,8 +5,7 @@ target = "xilinx"
syn_device = "xc6slx150t"
include_dirs=["../vme64x_bfm", "../2048Mb_ddr3", "../../../ip_cores/general-cores/sim"]
files = [ "main.sv",
"../../../ip_cores/adc_serdes.vhd"]
files = [ "main.sv"]
modules = { "local" : [ "../2048Mb_ddr3",
"../../rtl",
......
hdl/svec/syn/Manifest.py
View file @ e5e8da78
......@@ -8,9 +8,7 @@ syn_top = "svec_top_fmc_adc_100Ms"
syn_project = "svec_fmc_adc_100Ms.xise"
syn_tool = "ise"
files = [
"../svec_top_fmc_adc_100Ms.ucf",
"../../ip_cores/adc_serdes.vhd"]
files = ["../svec_top_fmc_adc_100Ms.ucf"]
modules = { "local" : ["../rtl",
"../../adc/rtl"],
......
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