- 15 Jul, 2020 1 commit
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Maciej Lipinski authored
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- 14 Jul, 2020 1 commit
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Jorge Machado authored
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- 13 Jul, 2020 2 commits
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Jorge Machado authored
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Jorge Machado authored
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- 14 May, 2020 7 commits
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Jorge Machado authored
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Jorge Machado authored
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Jorge Machado authored
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Jorge Machado authored
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Jorge Machado authored
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Jorge Machado authored
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Jorge Machado authored
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- 05 Mar, 2020 1 commit
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Maciej Lipinski authored
hdl/ip_cores/wr-cores: Fix missing commit issue See merge request !3
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- 04 Mar, 2020 1 commit
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Miguel Jimenez Lopez authored
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- 11 Dec, 2019 1 commit
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Maciej Lipinski authored
Klyone 20190412 fix copyright licenses See merge request !2
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- 04 Dec, 2019 3 commits
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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- 04 Nov, 2019 1 commit
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Maciej Lipinski authored
Sevensols wr starting kit update See merge request !1
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- 31 Oct, 2019 1 commit
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Benoit Rat authored
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- 12 Sep, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 04 Sep, 2019 2 commits
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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- 28 Aug, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 27 Aug, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 01 Aug, 2019 2 commits
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Miguel Jimenez Lopez authored
This latch provokes false interrupts in the DIO channel 4 for some bitstreams.
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Miguel Jimenez Lopez authored
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- 26 Jul, 2019 8 commits
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
- Legacy NIC/DIO This design instantiates the NIC and DIO cores externally. The WRPC fabric interface is connected to a fabric redirector core to allow the interconnection of a NIC module together with an Etherbone one. - DIO design with only NIC capabilities. - DIO design with only Etherbone capabilities.
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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- 11 Jul, 2019 1 commit
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Miguel Jimenez Lopez authored
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- 03 Apr, 2019 5 commits
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Javier Díaz authored
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Javier Díaz authored
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Benoit Rat authored
The first channel is set with 0 so that we force it to be output mode p/P & i/I mode will be only available for ch0, and D,d,1,0 will not be working (they will be seen as p/P).
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Miguel Jimenez Lopez authored
- OUT is enable when one pulse occurs or 1-PPS ch0 signal is enable. - TERM enable when any resistor termination channel is enable
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Miguel Jimenez Lopez authored
dio: Added DIO ch0 input support and hold DIO ch0 output as 1-PPS dedicated signal. Deleted PPS mode in DIO core
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