Commit b319d0cc authored by David Cussans's avatar David Cussans

* Adjusting timing between 40MHz clock and strobes in logic_clocks_rtl.vhd

* Incrementing version number ( now v24 )
parent 5444ee7a
......@@ -80,9 +80,9 @@ END ENTITY logic_clocks ;
--
ARCHITECTURE rtl OF logic_clocks IS
signal s_clk40 : std_logic;
constant C_NUM_STROBE_TAPS : positive := 3; --! Adjust to shift strobes relative to 40MHz clock edge
constant C_NUM_STROBE_TAPS : positive := 2; --! Adjust to shift strobes relative to 40MHz clock edge
signal s_clk40_delayed_160 : std_logic_vector(C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_4x strobe. Adjust length for correct alignment with incoming clock
signal s_clk40_delayed_320 : std_logic_vector(2*C_NUM_STROBE_TAPS downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
signal s_clk40_delayed_320 : std_logic_vector((2*C_NUM_STROBE_TAPS)+1 downto 0); --! Shift register used to generate clock_8x strobe. Adjust length for correct alignment with incoming clock
signal s_clk160 ,s_clk160_internal : std_logic;
signal s_clk320 , s_clk320_internal : std_logic;
......
......@@ -51,7 +51,7 @@ use work.ipbus.ALL;
entity top is
generic(
constant FW_VERSION : unsigned(31 downto 0):= X"1e000023"; -- Firmware revision. Remember to change this as needed.
constant FW_VERSION : unsigned(31 downto 0):= X"1e000024"; -- Firmware revision. Remember to change this as needed.
g_NUM_DUTS : positive := 4; -- <- was 3
g_NUM_TRIG_INPUTS :positive := 6;-- <- was 4
g_NUM_EDGE_INPUTS :positive := 6;-- <-- was 4
......
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