Commit fea36da1 authored by penacoba's avatar penacoba

Syn folder after manual cleanup to remove svn lock


git-svn-id: http://svn.ohwr.org/fmc-tdc@74 85dfdc96-de2c-444c-878d-45b388be74a9
parent a03c43a2
This diff is collapsed.
rm -r backup
rm -r coreip
rm identify.log
rm rpt_top_tdc.areasrr rpt_top_tdc_areasrr.htm
rm run_ise.tcl
rm run_options.txt scratchproject.prs
rm synplicity.ucf
rm fifo_32x512.ngc
rm fifo_64x512.ngc
rm syn_tdc.edf
rm syn_tdc.fse
rm syn_tdc.htm
rm syn_tdc.map
rm syn_tdc.ncf
rm syn_tdc_prepass.srd
rm syn_tdc.sap
rm syn_tdc.srd
rm syn_tdc.srl
rm syn_tdc.srm
rm syn_tdc.srr
rm syn_tdc.srs
rm syn_tdc.szr
rm syn_tdc.tlg
rm -r syntmp
rm -r xplace
rm syn_tdc.bld
rm syn_tdc.mrp
rm syn_tdc.ncd
rm syn_tdc.ngd
rm syn_tdc_ngdbuild.xrpt
rm syn_tdc.ngm
rm syn_tdc.ngo
rm syn_tdc.pcf
rm syn_tdc_summary.xml
rm syn_tdc_usage.xml
rm top_tdc_map.xrpt
rm top_tdc_par.xrpt
rm -r xlnx_auto_0_xdb
rm -r _xmsgs
rm netlist.lst
rm par_tdc.ncd
rm par_tdc.pad
rm par_tdc_pad.csv
rm par_tdc_pad.txt
rm par_tdc.par
rm par_tdc.ptwx
rm par_tdc.unroutes
rm par_tdc.xpi
rm par_usage_statistics.html
rm timing_report.twr
rm timing_report.twx
rm tdc.bgn
rm tdc.bit
rm tdc_bitgen.xwbt
rm tdc.drc
rm webtalk.log
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/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf 1321462749
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/blk_mem_circ_buff_v6_4.ngc 1321462688
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_64x512.ngc 1321462688
/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/fifo_32x512.ngc 1321462688
OK
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Release 13.3 - par O.76xd (lin64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Wed Nov 16 18:06:18 2011
All signals are completely routed.
WARNING:ParHelpers:361 - There are 10 loadless signals in this design. This design will cause Bitgen to issue DRC
warnings.
err_flag_i_IBUF
p_wr_req_i(0)_IBUF
p_wr_req_i(1)_IBUF
pll_refmon_i_IBUF
pll_sdo_i_IBUF
pll_status_i_IBUF
tdc_in_fpga_5_i_IBUF
tx_error_i_IBUF
vc_rdy_i(0)_IBUF
vc_rdy_i(1)_IBUF
PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=NO
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<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>7792</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>22101</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>22101</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>20680</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>39.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>46.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>82.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>98.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>144.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>153.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>249.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>249.3 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>250.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>257.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>4.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>5.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>6.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>11.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>12.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>2.8688</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
#### START OF AREA REPORT #####[
Part: XC6SLX45TFGG484-3 (Xilinx)
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.37 % Utilization)
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3462 100 %
MUXCY 892 100 %
XORCY 873 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5230 (52.80 % Utilization)
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.24 % Utilization)
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
<html><head><title></title></head><body><a name=TopSummary>
#### START OF AREA REPORT #####[<pre>
Part: XC6SLX45TFGG484-3 (Xilinx)
Click here to go to specific block report:
<a href="rpt_top_tdc_areasrr.htm#top_tdc"><h5 align="center">top_tdc</h5></a><br><a name=top_tdc>
-----------------------------------------------------------------------
######## Utilization report for Top level view: top_tdc ########
=======================================================================
SEQUENTIAL ELEMENTS
*******************
Name Total elements Utilization Notes
------------------------------------------------------
REGISTERS 4175 100 %
LATCHES 22 100 %
======================================================
Total SEQUENTIAL ELEMENTS in the block top_tdc: 4197 (42.37 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
COMBINATIONAL LOGIC
*******************
Name Total elements Utilization Notes
-----------------------------------------------------------------
LUTS 3462 100 %
MUXCY 892 100 %
XORCY 873 100 %
MULT18x18/MULT18x18S 3 100 %
SRL16 0 0 %
=================================================================
Total COMBINATIONAL LOGIC in the block top_tdc: 5230 (52.80 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
MEMORY ELEMENTS
***************
Name Total elements Utilization Notes
------------------------------------------------------
SYNC RAMS 1 100 %
======================================================
Total MEMORY ELEMENTS in the block top_tdc: 1 (0.01 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Name Total elements Number of bits Utilization Notes
--------------------------------------------------------------------
ROMS 0 0 0 %
====================================================================
Total in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
Distributed RAM
***************
Name Total elements Number of LUTs Utilization Notes
-------------------------------------------------------------------------------
DISTRIBUTED RAM 0 0 0 %
===============================================================================
Total Distributed RAM in the block top_tdc: 0 (0.00 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
IO PADS
*******
Name Total elements Utilization Notes
-------------------------------------------------
PADS 123 100 %
=================================================
Total IO PADS in the block top_tdc: 123 (1.24 % Utilization)
<a href="#TopSummary"><h5 align="right">Top</h5></a>
#### START OF Block RAM DETAILED REPORT ####
Total Block RAMs: 1
clks_rsts_mgment.un7_word_being_sent_0_0
----------------------------
----------------------------
#### END OF Block RAM DETAILED REPORT ####
##### END OF AREA REPORT #####]
</a></body></html>
#########################
### DEFINE VARIABLES ###
#########################
set DesignName "syn_tdc"
set FamilyName "SPARTAN6"
set DeviceName "XC6SLX45T"
set PackageName "FGG484"
set SpeedGrade "-3"
set TopModule "top_tdc"
set EdifFile "syn_tdc.edf"
if {![file exists $DesignName.ise]} {
project new $DesignName.ise
project set family $FamilyName
project set device $DeviceName
project set package $PackageName
project set speed $SpeedGrade
xfile add $EdifFile
if {[file exists synplicity.ucf]} {
xfile add synplicity.ucf
}
project set "Netlist Translation Type" "Timestamp"
project set "Other NGDBuild Command Line Options" "-verbose"
project set "Generate Detailed MAP Report" TRUE
project close
}
file delete -force $DesignName\_xdb
project open $DesignName.ise
process run "Implement Design" -force rerun_all
project close
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/run_options.txt
#-- Written on Wed Nov 16 17:58:07 2011
#project files
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "../src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "../src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "../src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "../src/rtl/free_counter.vhd"
add_file -vhdl -lib work "../src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "../src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "../src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "../src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "../src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "../src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "../src/rtl/data_engine.vhd"
add_file -vhdl -lib work "../src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "../src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "../src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "../src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "../src/rtl/top_tdc.vhd"
add_file -constraint "./tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./syn_tdc.edf"
impl -active "syn"
#-- Synopsys, Inc.
#-- Version D-2010.03
#-- Project file /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/scratchproject.prs
#-- Written on Wed Nov 16 17:58:07 2011
#project files
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.ngc"
add_file -include "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.ngc"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_pkg_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_32x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/xilinx_cores/fifo_64x512.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_n_to_1_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_ser_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_data_s2_se.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_des_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/serdes_1_to_n_clk_pll_s2_diff.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_decode32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/wbmaster32.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller_wb_slave.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/dma_controller.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/p2l_dma_master.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/l2p_arbiter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/gnum_core/gn4124_core_s6.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/ip_cores/mem_core/blk_mem_circ_buff_v6_4.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/tdc_core_pkg.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/free_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/incr_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/countdown_counter.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/clk_rst_managr.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/one_hz_gen.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/start_retrigger_control.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_formatting.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/data_engine.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_timecontrol_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/acam_databus_interface.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/circular_buffer.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/reg_ctrl.vhd"
add_file -vhdl -lib work "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/src/rtl/top_tdc.vhd"
add_file -constraint "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/tdc_syn_constraints.sdc"
#implementation: "syn"
impl -add /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn -type fpga
#
#implementation attributes
set_option -vlog_std v2001
set_option -num_critical_paths 5
set_option -project_relative_includes 1
set_option -include_path /afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/
#device options
set_option -technology Spartan6
set_option -part XC6SLX45T
set_option -package FGG484
set_option -speed_grade -3
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top_tdc"
# mapper_options
set_option -frequency 200
set_option -default_enum_encoding onehot
set_option -write_verilog 0
set_option -write_vhdl 0
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -retiming 0
set_option -update_models_cp 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# NFilter
set_option -popfeed 1
set_option -constprop 1
set_option -createhierarchy 0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0
#VIF options
set_option -write_vif 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "/afs/cern.ch/eng/eda/cds_users/gfernand/projects/tdc/syn/syn_tdc.edf"
impl -active "syn"
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 02000063
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 0000FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000F02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 01F0FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0
rrcmd w 0:80018 00000003
rrcmd w 0:8001C 00001FEA
rrcmd w 0:8002C 00FF0000
rrcmd w 0:80030 04000000
rrcmd w 0:80038 00000000
rrcmd r 0:80000
rrcmd r 0:80004
rrcmd r 0:80008
rrcmd r 0:8000C
rrcmd r 0:80010
rrcmd r 0:80014
rrcmd r 0:80018
rrcmd r 0:8001C
rrcmd r 0:8002C
rrcmd r 0:80030
rrcmd r 0:80038
rrcmd r 0:80020
rrcmd r 0:80024
rrcmd r 0:80028
rrcmd w 0:80000 01F0FC81
rrcmd w 0:80004 00000000
rrcmd w 0:80008 00000E02
rrcmd w 0:8000C 00000000
rrcmd w 0:80010 0200000F
rrcmd w 0:80014 000007D0