VME FMC carrier
BreakDown
Project Status:Main Features
- 2 Spartan6 FPGA
- One dedicated to system tasks (S-FPGA)
- One fully available for the user applications (A-FPGA)
- 2 LPC (Low Pin Count) FMC slots
- 40 user defined single ended (20 LVDS) connections from the A-FPGA to P2 available for rear plug-in units (transition modules)
- flexible clocking resources
- 1 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)
- 1 any rate I2C programmable crystal oscillator
- 1 Direct Digital Synthesizer (DDS)
- 3 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules
- Large amount of on board memory
- 2 completely independent 72Mbit ZBT SRAMS
- A 2Gbit DDR3
- 2 SPI 128Mbit flash proms for multiboot S-FPGA powerup configuration, storage of the A-FPGA firmware or of critical data
- Front panel connectivity
- 2 Small Formfactor Pluggable (SFP)
- 4 lemos configurable in all possible input/output combinations
- 1 e-SATA (to be confirmed)
Documentation
Functional specifications
- Approved document: link
Technical specifications
- schematic diagram: link
- overview presentation: link
- bill of material: https://www.ohwr.org/project/fmc-vme-carrier/uploads/c4ede9892c00f168f95e4eac59ca7c87/BOM.xls
- Design data EDMS EDA-02030
Status
Date | Event |
30-10-2009 | Start of project. |
24-03-2010 | PCB layout started |
10-05-2010 | Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies. |
11-05-2010 | All active components ordered. |
05-07-2010 | PCB layout review held. |
09-08-2010 | PCB layout good for production. |
01-09-2010 | Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand. |
23-06-2010 | Layout files received and being reviewed. |
15-09-2010 | PCB being produced at CERN. Expect assembled boards by mid October. |
Andrea Boccardi, Erik van der Bij - 15 September 2010