Skip to content

V
VME FMC Carrier VFC

Meeting20090506

Last edited by Andrea Boccardi
Page history

Minutes from the BI Technical Board of the 6th of May 2009

  • The signal distribution as defined on the P0 has to be kept with its buffering and distribution to the mezzanine scheme (JJ, Jose, David).
  • A similar argument is valid for the BLM designs but relative to the P2 (Bernd). The FMC standard power supply (12V and 3.3V) are not enough for analog designs or digital ones using ECL interfaces and deriving the required ones on the mezzanine not an option (JJ, Jose, David).
  • A one wire id chip should be mounted on each card. A PCB version ID should be implemented in HW.
  • The FMC mezzanines should be included in the JTAG chain for boundary scan testing, implying the design of a dummy mezzanine to be used at test time.
  • There should be at least 2 independent external SRAM banks to facilitate intensive processing (Andrea) The chosen SRAM should have minimized latency (Andrea)
  • A large memory block (DIMM?) should be present to store post-mortem data (David)
  • Would be nice to keep all the SW routines for the FPGA programming through the VME (Bernd)
  • The chosen main FPGA should have an equivalent number of gates at least double with respect to the Stratix S40 and the possible additional cost is a non issue (Bernd)