- 07 May, 2019 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 06 May, 2019 1 commit
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Grzegorz Daniluk authored
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- 29 Apr, 2019 10 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 26 Apr, 2019 1 commit
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Dimitris Lampridis authored
The previous implementation was introducing latches to the GN4124 core under Xilinx ISE. Tested and verified to work with the following SPEC-based reference designs: - WR - MT - WRTD
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- 25 Apr, 2019 1 commit
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Tristan Gingold authored
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- 24 Apr, 2019 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 17 Apr, 2019 1 commit
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Grzegorz Daniluk authored
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- 12 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 11 Apr, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 02 Apr, 2019 1 commit
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Tristan Gingold authored
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- 13 Feb, 2019 1 commit
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Dimitris Lampridis authored
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- 01 Feb, 2019 1 commit
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Dimitris Lampridis authored
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- 30 Jan, 2019 1 commit
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Dimitris Lampridis authored
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- 28 Jan, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 24 Jan, 2019 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 22 Jan, 2019 1 commit
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Tristan Gingold authored
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- 10 Jan, 2019 1 commit
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Dimitris Lampridis authored
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- 11 Dec, 2018 1 commit
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Dimitris Lampridis authored
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- 30 Nov, 2018 1 commit
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Tristan Gingold authored
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- 29 Nov, 2018 5 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Although not mentioned in section 5.2 of Wishbone B4 specification, when interfacing a pipelined master to a standard slave, it is also necessary to make sure that if the slave asserts ACK/ERR/RTY for more than one clock cycle (which a standard slave could do since, according to Rule 3.50 of Wishbone B4, "the slave deasserts ACK/ERR/RTY in response to the negation of STB"), the master will still only see a one cycle wide pulse.
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Dimitris Lampridis authored
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