Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
25ce764b
Commit
25ce764b
authored
May 24, 2017
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Move shell stuff to the root folder
parent
71431bfc
Hide whitespace changes
Inline
Side-by-side
Showing
12 changed files
with
11 additions
and
11 deletions
+11
-11
action.py
hdlmake/action/action.py
+1
-1
fetcher.py
hdlmake/fetch/fetcher.py
+1
-1
git.py
hdlmake/fetch/git.py
+1
-1
module.py
hdlmake/module/module.py
+1
-1
shell.py
hdlmake/shell.py
+0
-0
ise.py
hdlmake/tools/ise.py
+1
-1
isim.py
hdlmake/tools/isim.py
+1
-1
make_sim.py
hdlmake/tools/make_sim.py
+1
-1
make_syn.py
hdlmake/tools/make_syn.py
+1
-1
makefile.py
hdlmake/tools/makefile.py
+1
-1
quartus.py
hdlmake/tools/quartus.py
+1
-1
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+1
-1
No files found.
hdlmake/action/action.py
View file @
25ce764b
...
@@ -28,7 +28,7 @@ import os
...
@@ -28,7 +28,7 @@ import os
import
logging
import
logging
import
sys
import
sys
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.util.termcolor
import
colored
from
hdlmake.util.termcolor
import
colored
from
hdlmake
import
new_dep_solver
as
dep_solver
from
hdlmake
import
new_dep_solver
as
dep_solver
from
hdlmake
import
fetch
as
fetch_mod
from
hdlmake
import
fetch
as
fetch_mod
...
...
hdlmake/fetch/fetcher.py
View file @
25ce764b
...
@@ -23,7 +23,7 @@
...
@@ -23,7 +23,7 @@
from
__future__
import
absolute_import
from
__future__
import
absolute_import
import
os
import
os
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
class
Fetcher
(
object
):
class
Fetcher
(
object
):
...
...
hdlmake/fetch/git.py
View file @
25ce764b
...
@@ -24,7 +24,7 @@
...
@@ -24,7 +24,7 @@
from
__future__
import
absolute_import
from
__future__
import
absolute_import
import
os
import
os
from
hdlmake.util
import
path
as
path_utils
from
hdlmake.util
import
path
as
path_utils
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
import
logging
import
logging
from
.constants
import
GIT
from
.constants
import
GIT
from
.fetcher
import
Fetcher
from
.fetcher
import
Fetcher
...
...
hdlmake/module/module.py
View file @
25ce764b
...
@@ -33,7 +33,7 @@ import os
...
@@ -33,7 +33,7 @@ import os
import
logging
import
logging
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.util
import
path
as
path_mod
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.manifest_parser
import
ManifestParser
from
hdlmake.manifest_parser
import
ManifestParser
from
.content
import
ModuleContent
from
.content
import
ModuleContent
import
six
import
six
...
...
hdlmake/
util/
shell.py
→
hdlmake/shell.py
View file @
25ce764b
File moved
hdlmake/tools/ise.py
View file @
25ce764b
...
@@ -29,7 +29,7 @@ import logging
...
@@ -29,7 +29,7 @@ import logging
from
.make_syn
import
ToolSyn
from
.make_syn
import
ToolSyn
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
CDCFile
,
NGCFile
)
UCFFile
,
CDCFile
,
NGCFile
)
...
...
hdlmake/tools/isim.py
View file @
25ce764b
...
@@ -31,7 +31,7 @@ import os.path
...
@@ -31,7 +31,7 @@ import os.path
import
logging
import
logging
from
.make_sim
import
ToolSim
from
.make_sim
import
ToolSim
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
...
...
hdlmake/tools/make_sim.py
View file @
25ce764b
...
@@ -7,7 +7,7 @@ import string
...
@@ -7,7 +7,7 @@ import string
import
logging
import
logging
from
.makefile
import
ToolMakefile
from
.makefile
import
ToolMakefile
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
hdlmake.dep_file
import
DepFile
from
hdlmake.dep_file
import
DepFile
...
...
hdlmake/tools/make_syn.py
View file @
25ce764b
...
@@ -6,7 +6,7 @@ import logging
...
@@ -6,7 +6,7 @@ import logging
import
string
import
string
from
.makefile
import
ToolMakefile
from
.makefile
import
ToolMakefile
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
def
_check_synthesis_manifest
(
manifest_dict
):
def
_check_synthesis_manifest
(
manifest_dict
):
...
...
hdlmake/tools/makefile.py
View file @
25ce764b
...
@@ -28,7 +28,7 @@ import os
...
@@ -28,7 +28,7 @@ import os
import
logging
import
logging
import
six
import
six
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
class
ToolMakefile
(
object
):
class
ToolMakefile
(
object
):
...
...
hdlmake/tools/quartus.py
View file @
25ce764b
...
@@ -30,7 +30,7 @@ import logging
...
@@ -30,7 +30,7 @@ import logging
from
.make_syn
import
ToolSyn
from
.make_syn
import
ToolSyn
from
hdlmake.util
import
path
as
path_mod
from
hdlmake.util
import
path
as
path_mod
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
DPFFile
,
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
DPFFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
)
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
)
...
...
hdlmake/tools/sim_makefile_support.py
View file @
25ce764b
...
@@ -28,7 +28,7 @@ import os
...
@@ -28,7 +28,7 @@ import os
import
string
import
string
from
.make_sim
import
ToolSim
from
.make_sim
import
ToolSim
from
hdlmake
.util
import
shell
from
hdlmake
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
import
six
import
six
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment