Commits · cba64d4679ca270138857c11e85f66cd11d967bb · Projects / Hdlmake · Open Hardware Repository

03 Mar, 2017 3 commits
- Fix some issues related with Intel Quartus .qpf and .qsf files · cba64d46
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  cba64d46
- Use a separated TCL file for each synthesis stage · e758cc82
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  e758cc82
- Improve project management for Xilinx ISE · dc736d95
  Javier D. Garcia-Lasheras authored Mar 03, 2017
  
  dc736d95
19 Feb, 2017 1 commit
- Execute each Manifest from the folder in which it resides · f7598b52
  Javier D. Garcia-Lasheras authored Feb 19, 2017
  
  f7598b52
14 Feb, 2017 8 commits
- Fixing hierarchical support for Intel Quartus · 05e6060a
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  05e6060a
- Fixing hierarchical support for Modelsim · b5695a66
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  b5695a66
- Fixing hierarchical support for Xilinx ISim · ca39728f
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  ca39728f
- Fixing hierarchical support for Xilinx Vivado · 204210d6
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  204210d6
- Fixing hierarchical support for Xilinx ISE · 2a88a919
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  2a88a919
- Fixing hierarchical support for Icarus Verilog · b0b3990a
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  b0b3990a
- Fixing hierarchical support for GHDL · ceac87ea
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  ceac87ea
- First tests towards hierarchical behavior · 28035599
  Javier D. Garcia-Lasheras authored Feb 14, 2017
  
  28035599
21 Nov, 2016 2 commits
- Add syn & sim properties to Manifest.py and use it to provide custom settings to… · 03455340
  Javier D. Garcia-Lasheras authored Nov 21, 2016
```
Add syn & sim properties to Manifest.py and use it to provide custom settings to the newer Xilinx tools
```
  03455340
- Disable manual implementation compile order in ISE · 7eafb912
  Javier D. Garcia-Lasheras authored Nov 21, 2016
  
  7eafb912
17 Nov, 2016 5 commits
- Add System Exit exception handler to the Manifest parser · 12c7799b
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  12c7799b
- Add VHDL and Verilog template files support to Vivado · ec10c20b
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  ec10c20b
- Add RAM file support to Vivado · 92c32a9f
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  92c32a9f
- Add Xilinx Coefficient and Memory Initialization files · 3285708c
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  3285708c
- Hack a known Vivado issue by using IS_GLOBAL_INCLUDE · 879eca7f
  Javier D. Garcia-Lasheras authored Nov 17, 2016
  
  879eca7f
24 Sep, 2016 2 commits
- Launch Vivado in TCL mode · 6255c9ba
  Javier D. Garcia-Lasheras authored Sep 24, 2016
  
  6255c9ba
- Add support for Xilinx XDC and XCI files on Vivado · 42ddedf5
  Javier D. Garcia-Lasheras authored Sep 24, 2016
  
  42ddedf5
19 Sep, 2016 1 commit
- Bump version to 3.0 · 0d6f5be2
  Javier D. Garcia-Lasheras authored Sep 19, 2016
  
  0d6f5be2
07 Sep, 2016 4 commits
- Fix ISim not getting the right 'ini' file · 66d9f8e8
  Javier D. Garcia-Lasheras authored Sep 07, 2016
  
  66d9f8e8
- Some minor fixes to be 100% PEP8 compliant · 32141242
  Javier D. Garcia-Lasheras authored Sep 07, 2016
  
  32141242
- Adapt the synthesis tools to use the new pure Python 'which' function · 6bcc2084
  Javier D. Garcia-Lasheras authored Sep 07, 2016
  
  6bcc2084
- which: use pure python code to find executable · 0a6230de
  Piotr Miedzik authored Sep 07, 2016
  
  0a6230de
26 Aug, 2016 1 commit
- Add tag support to Quartus · a02f00dc
  Piotr Miedzik authored Aug 26, 2016
  
  a02f00dc
19 Aug, 2016 1 commit
- Move 'check_tool' method from Env to Tools package · b65b0cf5
  Javier D. Garcia-Lasheras authored Aug 19, 2016
  
  b65b0cf5
18 Aug, 2016 1 commit
- A more straighforward way of using the fetcher's backends · ca7cdc4b
  Javier D. Garcia-Lasheras authored Aug 18, 2016
  
  ca7cdc4b
17 Aug, 2016 11 commits
- Create an appropriated parser instance for VHDLFile and VerilogFile · f1c0bc62
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  f1c0bc62
- fix PEP8 issue: too many blank lines at '__main__.py' · a0fad54f
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  a0fad54f
- Split the load_tool function at main into different functions for simulation and synthesis · 17961e27
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  17961e27
- Line too long at 'module.py' · 3d2b3919
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  3d2b3919
- Group the files' Class by vendor in 'srcfile.py' · ea29eb08
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  ea29eb08
- Enable the '--reverse' option in 'list-files' action · 607c041a
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  607c041a
- Add a '--top' option to list-files to build a file hierarchy list · 4d712d8d
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  4d712d8d
- Purge unused method 'get_module_by_path' · a774d263
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  a774d263
- Change the way we initialize the pool's environment · 9163130b
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  9163130b
- Fix some issues with imports · 07f1ce6a
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  07f1ce6a
- The following public method is not used: 'get_fetchable_modules' · 9ed1e91e
  Javier D. Garcia-Lasheras authored Aug 17, 2016
  
  9ed1e91e