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nanoFIP - Gateware
Commit afec7029 authored by egousiou's avatar egousiou
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changes in slone mode to include PDU_TYPE, Length, mps bytes on production. 

changes on treatment of reset variable
temp alternative file for wf_reset_unit that assumes a PoR input
small changes regarding reseting the rx_tx_osc unit 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@96 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 7a2e56fc
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DualClkRAM.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file DualClkRAM.vhd --! @file DualClkRAM.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! Standard library --! Standard library
library IEEE; library IEEE;
...@@ -20,8 +28,6 @@ use PROASIC3.all; ...@@ -20,8 +28,6 @@ use PROASIC3.all;
-- -- -- --
-- DualClkRAM -- -- DualClkRAM --
-- -- -- --
-- CERN, BE/CO/HT --
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- --
...@@ -31,7 +37,7 @@ use PROASIC3.all; ...@@ -31,7 +37,7 @@ use PROASIC3.all;
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- --
--! @date 16/08/2010 --! @date 16/08/2010
...@@ -71,14 +77,14 @@ entity DualClkRAM is ...@@ -71,14 +77,14 @@ entity DualClkRAM is
port( port(
-- INPUTS -- INPUTS
-- Inpouts concerning port A -- Inpouts concerning port A
DINA : in std_logic_vector (7 downto 0); --! data in A DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector (8 downto 0); --! address A ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B -- may be indipendant of clock B
-- Inpouts concerning port B -- Inpouts concerning port B
DINB : in std_logic_vector (7 downto 0); --! data in B DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector (8 downto 0); --! address B ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A -- may be indipendant of clock A
...@@ -87,10 +93,10 @@ entity DualClkRAM is ...@@ -87,10 +93,10 @@ entity DualClkRAM is
-- OUTPUTS -- OUTPUTS
-- Output concerning port A -- Output concerning port A
DOUTA : out std_logic_vector (7 downto 0); --! data out A DOUTA : out std_logic_vector (7 downto 0);--! data out A
-- Output concerning port B -- Output concerning port B
DOUTB : out std_logic_vector (7 downto 0) --! data out B DOUTB : out std_logic_vector (7 downto 0) --! data out B
); );
end DualClkRAM; end DualClkRAM;
......
nanofip.vhd
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tmp_wf_reset_unit_with_PoR.vhd 0 → 100644
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wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ afec7029
--________________________________________________________________________________________________|
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @file wf_DualClkRAM_clka_rd_clkb_wr.vhd --! @file WF_DualClkRAM_clka_rd_clkb_wr.vhd |
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Standard library --! Standard library
library IEEE; library IEEE;
-- Standard packages --! Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_DualClkRAM_clka_rd_clkb_wr -- -- WF_DualClkRAM_clka_rd_clkb_wr --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_DualClkRAM_clka_rd_clkb_wr.vhd -- unit name WF_DualClkRAM_clka_rd_clkb_wr.vhd
-- --
-- --
--! @brief The unit provides, transparently to the outside world, the memory triplication. --! @brief The unit provides, transparently to the outside world, the memory triplication.
...@@ -27,7 +33,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -27,7 +33,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- --
--! @date 08/2010 --! @date 08/2010
...@@ -58,10 +64,10 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -58,10 +64,10 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_DualClkRAM_clka_rd_clkb_wr --! Entity declaration for WF_DualClkRAM_clka_rd_clkb_wr
--================================================================================================= --=================================================================================================
entity wf_DualClkRAM_clka_rd_clkb_wr is entity WF_DualClkRAM_clka_rd_clkb_wr is
generic (C_RAM_DATA_LGTH : integer; -- length of data word generic (C_RAM_DATA_LGTH : integer; -- length of data word
C_RAM_ADDR_LGTH : integer); -- memory depth C_RAM_ADDR_LGTH : integer); -- memory depth
...@@ -77,13 +83,13 @@ entity wf_DualClkRAM_clka_rd_clkb_wr is ...@@ -77,13 +83,13 @@ entity wf_DualClkRAM_clka_rd_clkb_wr is
data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0) data_A_o : out std_logic_vector (C_RAM_DATA_LGTH -1 downto 0)
); );
end wf_DualClkRAM_clka_rd_clkb_wr; end WF_DualClkRAM_clka_rd_clkb_wr;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture syn of wf_DualClkRAM_clka_rd_clkb_wr is architecture syn of WF_DualClkRAM_clka_rd_clkb_wr is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: component DualClkRam declaration --!@brief: component DualClkRam declaration
......
wf_VAR_RDY_generator.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_VAR_RDY_generator.vhd --! @file WF_VAR_RDY_generator.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,15 +14,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,15 +14,15 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_VAR_RDY_generator -- -- WF_VAR_RDY_generator --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- --
--! @brief Generation of the nanoFIP output signals VAR1_RDY, VAR2_RDY, VAR3_RDY according to --! @brief Generation of the nanoFIP output signals VAR1_RDY, VAR2_RDY, VAR3_RDY according to
--! the variable that is being treated (wf_engine_control signal) --! the variable that is being treated (WF_engine_control signal)
-- --
-- --
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
...@@ -46,50 +46,61 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -46,50 +46,61 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
-- -- EG treatment of reset vars
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
--! @todo --! @todo
--! -> --! -> rename the unit to include actions for var reset.
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_VAR_RDY_generator --! Entity declaration for WF_VAR_RDY_generator
--================================================================================================= --=================================================================================================
entity wf_VAR_RDY_generator is entity WF_VAR_RDY_generator is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
slone_i : in std_logic; --! Stand-alone mode slone_i : in std_logic; --! Stand-alone mode
subs_i : in std_logic_vector (7 downto 0); --! Station address
-- Signal from the WF_reset_unit unit
nFIP_urst_i : in std_logic; --! internal reset
-- Signal from the wf_reset_unit unit -- Signals from WF_cons_frame_validator
nFIP_u_rst_i : in std_logic; --! internal reset cons_frame_ok_p_i : in std_logic; --!pulse after a valid consumed frame
var_i : in t_var; --! variable that is being treated
-- Signals from wf_engine_control -- Signals from WF_cons_bytes_from_rx
cons_frame_ok_p_i : in std_logic; --! pulse after a valid consumed frame rx_var_rst_byte_1_i : in std_logic_vector (7 downto 0); --! First & second data bytes of a
var_i : in t_var; --! variable that is being treated rx_var_rst_byte_2_i : in std_logic_vector (7 downto 0); --! reset variable
-- OUTPUT -- OUTPUT
-- Signal to wf_engine_control -- nanoFIP output signals
var1_rdy_o : out std_logic; var1_rdy_o : out std_logic;
var2_rdy_o : out std_logic; var2_rdy_o : out std_logic;
var3_rdy_o : out std_logic var3_rdy_o : out std_logic;
-- Signals for the WF_reset_unit
assert_RSTON_p_o : out std_logic;
rst_nFIP_and_FD_p_o : out std_logic
); );
end entity wf_VAR_RDY_generator; end entity WF_VAR_RDY_generator;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_VAR_RDY_generator is architecture rtl of WF_VAR_RDY_generator is
signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic; signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
signal s_rst_nFIP_and_FD, s_assert_RSTON : std_logic;
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -130,7 +141,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic; ...@@ -130,7 +141,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
VAR_RDY_Generation: process(uclk_i) VAR_RDY_Generation: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
var1_rdy_o <= '0'; var1_rdy_o <= '0';
var2_rdy_o <= '0'; var2_rdy_o <= '0';
var3_rdy_o <= '0'; var3_rdy_o <= '0';
...@@ -207,7 +218,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic; ...@@ -207,7 +218,7 @@ signal s_var1_received, s_var2_received, cons_frame_ok_p_d1 : std_logic;
Cons_frame_ok_p_delay: process(uclk_i) Cons_frame_ok_p_delay: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
cons_frame_ok_p_d1 <= '0'; cons_frame_ok_p_d1 <= '0';
else else
cons_frame_ok_p_d1 <= cons_frame_ok_p_i; cons_frame_ok_p_d1 <= cons_frame_ok_p_i;
...@@ -215,6 +226,50 @@ Cons_frame_ok_p_delay: process(uclk_i) ...@@ -215,6 +226,50 @@ Cons_frame_ok_p_delay: process(uclk_i)
end if; end if;
end process; end process;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_rst_nFIP_and_FD: signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_assert_RSTON: signals that the 2nd byte of a consumed
--! reset var contains the station address
Reset_Signals: process (uclk_i)
begin
if rising_edge(uclk_i) then
if nFIP_urst_i = '1' then
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
else
if var_i = var_rst then
if rx_var_rst_byte_1_i = subs_i then
s_rst_nFIP_and_FD <= '1'; -- rst_nFIP_and_FD_o stays asserted until
end if; -- the end of the current rp_dat frame
if rx_var_rst_byte_2_i = subs_i then
s_assert_RSTON <= '1'; -- assert_RSTON_o stays asserted until
end if; -- the end of the current rp_dat frame
else
s_rst_nFIP_and_FD <= '0';
s_assert_RSTON <= '0';
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
rst_nFIP_and_FD_p_o <= '1' when s_rst_nFIP_and_FD = '1' and cons_frame_ok_p_d1= '1'
else '0';
assert_RSTON_p_o <= '1' when s_assert_RSTON = '1' and cons_frame_ok_p_d1= '1'
else '0';
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
......
wf_bits_to_txd.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_bits_to_txd.vhd --! @file WF_bits_to_txd.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_bits_to_txd -- -- WF_bits_to_txd --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -59,20 +59,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -59,20 +59,20 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_bits_to_txd --! Entity declaration for WF_bits_to_txd
--================================================================================================= --=================================================================================================
entity wf_bits_to_txd is entity WF_bits_to_txd is
generic(C_TXCLKBUFFLENTGTH: natural); generic(C_TXCLKBUFFLENTGTH: natural);
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_tx -- Signals from WF_tx
txd_bit_index_i : in unsigned(4 downto 0); txd_bit_index_i : in unsigned(4 downto 0);
data_byte_manch_i : in std_logic_vector (15 downto 0); data_byte_manch_i : in std_logic_vector (15 downto 0);
crc_byte_manch_i : in std_logic_vector (31 downto 0); crc_byte_manch_i : in std_logic_vector (31 downto 0);
...@@ -83,23 +83,23 @@ entity wf_bits_to_txd is ...@@ -83,23 +83,23 @@ entity wf_bits_to_txd is
stop_transmission_i : in std_logic; stop_transmission_i : in std_logic;
-- Signals for the receiver wf_tx_rx_osc -- Signals for the receiver WF_tx_rx_osc
tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0); tx_clk_p_buff_i : in std_logic_vector (C_TXCLKBUFFLENTGTH-1 downto 0);
--! clk for transmission synchronization --! clk for transmission synchronization
-- OUTPUTS -- OUTPUTS
-- Signal to wf_prod_bytes_to_tx -- Signal to WF_prod_bytes_to_tx
txd_o : out std_logic; txd_o : out std_logic;
tx_enable_o : out std_logic tx_enable_o : out std_logic
); );
end entity wf_bits_to_txd; end entity WF_bits_to_txd;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_bits_to_txd is architecture rtl of WF_bits_to_txd is
signal s_start_tx_enable, s_tx_enable : std_logic; signal s_start_tx_enable, s_tx_enable : std_logic;
...@@ -117,7 +117,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic; ...@@ -117,7 +117,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic;
Bits_Delivery: process(uclk_i) Bits_Delivery: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
txd_o <= '0'; txd_o <= '0';
else else
...@@ -158,7 +158,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic; ...@@ -158,7 +158,7 @@ signal s_start_tx_enable, s_tx_enable : std_logic;
tx_enable_manager: process(uclk_i) tx_enable_manager: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
tx_enable_o <= '0'; tx_enable_o <= '0';
s_start_tx_enable <= '0'; s_start_tx_enable <= '0';
......
wf_cons_bytes_from_rx.vhd
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wf_cons_frame_validator.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_cons_frame_validator.vhd --! @file WF_cons_frame_validator.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_cons_frame_validator -- -- WF_cons_frame_validator --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -56,37 +56,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -56,37 +56,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_cons_frame_validator --! Entity declaration for WF_cons_frame_validator
--================================================================================================= --=================================================================================================
entity wf_cons_frame_validator is entity WF_cons_frame_validator is
port ( port (
-- INPUTS -- INPUTS
-- Signals from the wf_cons_bytes_from_rx unit -- Signals from the WF_cons_bytes_from_rx unit
rx_Ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte rx_Ctrl_byte_i : in std_logic_vector (7 downto 0); --! received Ctrl byte
rx_PDU_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte rx_PDU_byte_i : in std_logic_vector (7 downto 0); --! received PDU_TYPE byte
rx_Length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte rx_Length_byte_i : in std_logic_vector (7 downto 0); --! received Length byte
-- Signal from the wf_rx unit -- Signal from the WF_rx unit
rx_FSS_CRC_FES_viol_ok_p_i : in std_logic; --! indication that CRC and FES have rx_FSS_CRC_FES_viol_ok_p_i : in std_logic; --! indication that CRC and FES have
-- Signals from wf_engine_control -- Signals from WF_engine_control
var_i: in t_var; var_i: in t_var;
rx_byte_index_i : in unsigned(7 downto 0); rx_byte_index_i : in unsigned(7 downto 0);
-- OUTPUT -- OUTPUT
-- Signal to wf_engine_control -- Signal to WF_engine_control
cons_frame_ok_p_o : out std_logic cons_frame_ok_p_o : out std_logic
); );
end entity wf_cons_frame_validator; end entity WF_cons_frame_validator;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_cons_frame_validator is architecture rtl of WF_cons_frame_validator is
signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic; signal s_rx_ctrl_byte_ok, s_rx_PDU_byte_ok, s_rx_length_byte_ok : std_logic;
......
wf_crc.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_crc.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_crc.vhd
---------------------------------------------------------------------------------------------------
--! Standard library --! Standard library
library IEEE; library IEEE;
...@@ -9,15 +17,16 @@ library IEEE; ...@@ -9,15 +17,16 @@ library IEEE;
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions use IEEE.NUMERIC_STD.all; --! conversion functions
--! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_crc -- -- WF_crc --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_crc -- unit name WF_crc
-- --
-- --
--! @brief The unit includes the modules for the generation of the CRC of serialized data, --! @brief The unit includes the modules for the generation of the CRC of serialized data,
...@@ -25,7 +34,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -25,7 +34,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- --
--! @date 08/2010 --! @date 08/2010
...@@ -59,14 +68,14 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -59,14 +68,14 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_crc --! Entity declaration for WF_crc
--================================================================================================= --=================================================================================================
entity wf_crc is entity WF_crc is
generic(c_GENERATOR_POLY_length : natural := 16); generic(c_GENERATOR_POLY_length : natural);
port ( port (
-- INPUTS -- INPUTS
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
start_CRC_p_i : in std_logic; --! signaling the beginning of the CRC calculation start_CRC_p_i : in std_logic; --! signaling the beginning of the CRC calculation
data_bit_i : in std_logic; --! incoming data bit stream data_bit_i : in std_logic; --! incoming data bit stream
data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled data_bit_ready_p_i : in std_logic; --! signaling that data_bit_i can be sampled
...@@ -74,24 +83,15 @@ port ( ...@@ -74,24 +83,15 @@ port (
-- OUTPUTS -- OUTPUTS
CRC_ok_p : out std_logic; --! signaling of a correct received CRC syndrome CRC_ok_p : out std_logic; --! signaling of a correct received CRC syndrome
CRC_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC CRC_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated CRC
-- 2 bytes
); );
end entity wf_crc; end entity WF_crc;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_crc is architecture rtl of WF_crc is
--! shift register xor mask
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) :=
"0001110111001111";
--! CRC check mask
constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011";
signal s_crc_bit_ready_p : std_logic; signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0); signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
...@@ -126,7 +126,7 @@ end generate; ...@@ -126,7 +126,7 @@ end generate;
CRC_calculation: process(uclk_i) CRC_calculation: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_q <= (others => '1'); -- register initialization s_q <= (others => '1'); -- register initialization
-- (initially preset, according to annex A) -- (initially preset, according to annex A)
......
wf_decr_counter.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_decr_counter.vhd --! @file WF_decr_counter.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_decr_counter -- -- WF_decr_counter --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -52,18 +52,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -52,18 +52,18 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_decr_counter --! Entity declaration for WF_decr_counter
--================================================================================================= --=================================================================================================
entity wf_decr_counter is entity WF_decr_counter is
generic(counter_length : natural); generic(counter_length : natural);
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from any unit -- Signals from any unit
counter_top : in unsigned (counter_length-1 downto 0); --! load value counter_top : in unsigned (counter_length-1 downto 0); --! load value
...@@ -76,13 +76,13 @@ entity wf_decr_counter is ...@@ -76,13 +76,13 @@ entity wf_decr_counter is
counter_o : out unsigned (counter_length-1 downto 0);--! counter counter_o : out unsigned (counter_length-1 downto 0);--! counter
counter_is_zero_o : out std_logic --! empty counter indication counter_is_zero_o : out std_logic --! empty counter indication
); );
end entity wf_decr_counter; end entity WF_decr_counter;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_decr_counter is architecture rtl of WF_decr_counter is
signal s_counter : unsigned(counter_length-1 downto 0); signal s_counter : unsigned(counter_length-1 downto 0);
...@@ -95,7 +95,7 @@ signal s_counter : unsigned(counter_length-1 downto 0); ...@@ -95,7 +95,7 @@ signal s_counter : unsigned(counter_length-1 downto 0);
Decr_Counter: process(uclk_i) Decr_Counter: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
else else
......
wf_engine_control.vhd
View file @ afec7029
This diff is collapsed.
wf_incr_counter.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_incr_counter.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
--------------------------------------------------------------------------------------------------
--! @file WF_incr_counter.vhd
---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -11,18 +19,16 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -11,18 +19,16 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_incr_counter -- -- WF_incr_counter --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- --
--! @brief Synchronous increasing counter with a reset and an increase enable signal; --! @brief Fully synchronous increasing counter with a reset, a reinitialise & an enable signal
-- --
-- --
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch) --! Evangelia Gousiou (evangelia.gousiou@cern.ch)
-- --
-- --
--! @date 06/2010 --! @date 06/2010
...@@ -52,51 +58,53 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -52,51 +58,53 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_incr_counter --! Entity declaration for WF_incr_counter
--================================================================================================= --=================================================================================================
entity wf_incr_counter is entity WF_incr_counter is
generic(counter_length : natural); generic(counter_length : natural);
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from any unit -- Signals from any unit
reset_counter_i : in std_logic; --! resets counter to 0 reinit_counter_i : in std_logic; --! reinitializes counter to 0
incr_counter_i: in std_logic; --! increment enable incr_counter_i: in std_logic; --! increment enable
-- OUTPUT -- OUTPUT
-- Signal to any unit -- Signal to any unit
counter_o : out unsigned(counter_length-1 downto 0) --! counter counter_o : out unsigned(counter_length-1 downto 0); --! counter
counter_is_full_o : out std_logic --! all counter bits at '1'
); );
end entity wf_incr_counter; end entity WF_incr_counter;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_incr_counter is architecture rtl of WF_incr_counter is
signal s_counter : unsigned(counter_length-1 downto 0); signal s_counter, s_counter_full : unsigned(counter_length-1 downto 0);
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
--================================================================================================= --=================================================================================================
begin begin
s_counter_full <= (others => '1');
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
Incr_Counter: process(uclk_i) Incr_Counter: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
elsif reset_counter_i = '1' then elsif reinit_counter_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
elsif incr_counter_i = '1' then elsif incr_counter_i = '1' then
...@@ -106,7 +114,9 @@ signal s_counter : unsigned(counter_length-1 downto 0); ...@@ -106,7 +114,9 @@ signal s_counter : unsigned(counter_length-1 downto 0);
end if; end if;
end process; end process;
counter_o <= s_counter; counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter= s_counter_full
else '0';
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
......
wf_inputs_synchronizer.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_inputs_synchronizer.vhd --! @file WF_inputs_synchronizer.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_inputs_synchronizer -- -- WF_inputs_synchronizer --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -56,21 +56,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -56,21 +56,21 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_inputs_synchronizer --! Entity declaration for WF_inputs_synchronizer
--================================================================================================= --=================================================================================================
entity wf_inputs_synchronizer is entity WF_inputs_synchronizer is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- User Interface WISHBONE slave -- User Interface WISHBONE slave
wbclk_i : in std_logic; --! WISHBONE clock wbclk_i : in std_logic; --! WISHBONE clock
wb_rst_a_i : in std_logic; --! WISHBONE reset wb_rst_a_i : in std_logic; --! WISHBONE reset
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Rest of input signals -- Rest of input signals
rstin_a_i : in std_logic; rstin_a_i : in std_logic;
...@@ -95,8 +95,8 @@ entity wf_inputs_synchronizer is ...@@ -95,8 +95,8 @@ entity wf_inputs_synchronizer is
-- OUTPUTS -- OUTPUTS
-- Signals to nanofip -- Signals to nanofip
u_rsti_o : out std_logic; -- rstin_a_i synchronized to uclk rsti_o : out std_logic; -- rstin_a_i synchronized to uclk
-- wb_rsti_o : out std_logic; -- rstin_a_i synchronized to wbclk urst_r_edge_o : out std_logic;
slone_o : out std_logic; slone_o : out std_logic;
nostat_o : out std_logic; nostat_o : out std_logic;
fd_wdgn_o : out std_logic; fd_wdgn_o : out std_logic;
...@@ -121,13 +121,13 @@ entity wf_inputs_synchronizer is ...@@ -121,13 +121,13 @@ entity wf_inputs_synchronizer is
c_id_o : out std_logic_vector(3 downto 0); c_id_o : out std_logic_vector(3 downto 0);
p3_lgth_o : out std_logic_vector(2 downto 0) p3_lgth_o : out std_logic_vector(2 downto 0)
); );
end entity wf_inputs_synchronizer; end entity WF_inputs_synchronizer;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_inputs_synchronizer is architecture rtl of WF_inputs_synchronizer is
signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic; signal s_wb_we_d3, s_wb_cyc_d1, s_wb_cyc_d2, s_wb_cyc_d3, s_fd_rxd_f_edge : std_logic;
signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic; signal s_var1_access_d1, s_var2_access_d1, s_var3_access_d1, s_fd_rxd_r_edge : std_logic;
...@@ -136,8 +136,9 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -136,8 +136,9 @@ architecture rtl of wf_inputs_synchronizer is
signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic; signal s_wb_stb_d1, s_wb_stb_d2, s_wb_stb_d3, s_wb_stb_d4, s_wb_we_d1, s_wb_we_d2 : std_logic;
signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0); signal s_mid_d1, s_mid_d2, s_mid_d3, s_cid_d1, s_cid_d2, s_cid_d3 : std_logic_vector(3 downto 0);
signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3 : std_logic_vector(2 downto 0); signal s_fd_txer_d3, s_fd_wdgn_d3, s_fd_rxd_d3 : std_logic_vector(2 downto 0);
signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3, s_u_rst_d3 : std_logic_vector(2 downto 0); signal s_p3_lgth_d1, s_p3_lgth_d2, s_p3_lgth_d3 : std_logic_vector(2 downto 0);
signal s_nostat_d3, s_slone_d3, s_rsti_w_d3 : std_logic_vector(2 downto 0); signal s_u_rst_d3 : std_logic_vector(3 downto 0);--:= "0000";
signal s_nostat_d3, s_slone_d3 : std_logic_vector(2 downto 0);
signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0); signal s_wb_adr_d1, s_wb_adr_d2, s_wb_adr_d3 : std_logic_vector(9 downto 0);
signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0); signal s_rate_d1, s_rate_d2, s_rate_d3 : std_logic_vector(1 downto 0);
signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0); signal s_subs_d1, s_subs_d2, s_subs_d3 : std_logic_vector(7 downto 0);
...@@ -157,32 +158,19 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -157,32 +158,19 @@ architecture rtl of wf_inputs_synchronizer is
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
s_u_rst_d3 <= s_u_rst_d3 (1 downto 0) & (not rstin_a_i); s_u_rst_d3 <= s_u_rst_d3 (2 downto 0) & (not rstin_a_i);
end if; end if;
end process; end process;
u_rsti_o <= s_u_rst_d3(2); -- active high rsti_o <= s_u_rst_d3(2); -- active high
urst_r_edge_o <= not s_u_rst_d3(3) and s_u_rst_d3(2);
---------------------------------------------------------------------------------------------------
-- rstin_synchronisation_with_wclk: process (wbclk_i)
-- begin
-- if rising_edge(wbclk_i) then
-- s_wb_rsti_d3 <= s_wb_rsti_d3 (1 downto 0) & (not rstin_a_i);
-- end if;
-- end process;
-- rsti_wb_o <= s_wb_rsti_d3(2); -- active high
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
User_interf_general_signals_synchronisation: process (uclk_i) User_interf_general_signals_synchronisation: process (uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_slone_d3 <= (others => '0'); s_slone_d3 <= (others => '0');
s_nostat_d3 <= (others => '0'); s_nostat_d3 <= (others => '0');
else else
...@@ -201,7 +189,7 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -201,7 +189,7 @@ architecture rtl of wf_inputs_synchronizer is
fieldrive_inputs_synchronisation: process(uclk_i) fieldrive_inputs_synchronisation: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_fd_rxd_d3 <= (others => '0'); s_fd_rxd_d3 <= (others => '0');
s_fd_wdgn_d3 <= (others => '0'); s_fd_wdgn_d3 <= (others => '0');
s_fd_txer_d3 <= (others => '0'); s_fd_txer_d3 <= (others => '0');
...@@ -230,7 +218,7 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -230,7 +218,7 @@ architecture rtl of wf_inputs_synchronizer is
VAR_ACC_synchronisation: process(uclk_i) VAR_ACC_synchronisation: process(uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_var1_access_d1 <= '0'; s_var1_access_d1 <= '0';
s_var1_access_d2 <= '0'; s_var1_access_d2 <= '0';
s_var1_access_d3 <= '0'; s_var1_access_d3 <= '0';
...@@ -321,7 +309,7 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -321,7 +309,7 @@ architecture rtl of wf_inputs_synchronizer is
Slone_dat_i_synchronization: process(uclk_i) Slone_dat_i_synchronization: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_slone_dati_d1 <= (others => '0'); s_slone_dati_d1 <= (others => '0');
s_slone_dati_d2 <= (others => '0'); s_slone_dati_d2 <= (others => '0');
s_slone_dati_d3 <= (others => '0'); s_slone_dati_d3 <= (others => '0');
...@@ -340,7 +328,7 @@ architecture rtl of wf_inputs_synchronizer is ...@@ -340,7 +328,7 @@ architecture rtl of wf_inputs_synchronizer is
WFIP_settings_synchronisation: process(uclk_i) WFIP_settings_synchronisation: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_rate_d1 <= (others => '0'); s_rate_d1 <= (others => '0');
s_rate_d2 <= (others => '0'); s_rate_d2 <= (others => '0');
s_rate_d3 <= (others => '0'); s_rate_d3 <= (others => '0');
......
wf_manch_code_viol_check.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_decr_counter.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_decr_counter.vhd
---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,21 +22,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,21 +22,19 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_manch_code_viol_check -- -- WF_manch_code_viol_check --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- --
--! @brief The unit follows the incoming serial signal and outputs a pulse --! @brief The unit follows an incoming serial signal and outputs a pulse
--! if a manchester 2 code violation is detected. --! if a manchester 2 code violation is detected.
--! It is assumed that a violation happens if after half reception period --! It is assumed that a violation happens if after half reception period
--! plus 2 uclck periods, the incoming signal has not had a transition. --! plus 2 uclck periods, the incoming signal has not had a transition.
-- --
-- --
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- --
--! @date 06/2010 --! @date 06/2010
...@@ -58,37 +64,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -58,37 +64,37 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_manch_code_viol_check --! Entity declaration for WF_manch_code_viol_check
--================================================================================================= --=================================================================================================
entity wf_manch_code_viol_check is entity WF_manch_code_viol_check is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_rx -- Signals from WF_rx
serial_input_signal_i : in std_logic; serial_input_signal_i : in std_logic; --! input signal
sample_bit_p_i : in std_logic; sample_bit_p_i : in std_logic; --! pulse for the sampling of a new bit
sample_manch_bit_p_i : in std_logic; sample_manch_bit_p_i : in std_logic; --! pulse for the sampling of a new manch. bit
-- OUTPUTS -- OUTPUTS
-- Signal to wf_rx -- Signal to WF_rx
manch_code_viol_p_o : out std_logic manch_code_viol_p_o : out std_logic --! pulse indicating a code violation
); );
end entity wf_manch_code_viol_check; end entity WF_manch_code_viol_check;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_manch_code_viol_check is architecture rtl of WF_manch_code_viol_check is
signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input_signal_d : std_logic; signal s_sample_bit_p_d1,s_sample_bit_p_d2,s_check_code_viol_p,s_serial_input_signal_d : std_logic;
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -99,9 +105,9 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input ...@@ -99,9 +105,9 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief synchronous process Check_Code_Violations:in order to check the existance code violations --!@brief Synchronous process Check_Code_Violations:in order to check the existance code violations
--! the input signal is delayed by half reception period. --! the input signal is delayed by half reception period.
--! The signal s_check_code_viol_p is a pulse with period the reception period. The pulse occurs --! The signal check_code_viol_p is a pulse with period the reception period. The pulse occurs
--! 2 uclk periods after a manch. transition is expected. --! 2 uclk periods after a manch. transition is expected.
--! As the following drawing roughly indicates, a violation exists if the signal and its delayed --! As the following drawing roughly indicates, a violation exists if the signal and its delayed
--! version are identical on the s_check_code_viol_p moments. --! version are identical on the s_check_code_viol_p moments.
...@@ -114,7 +120,7 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input ...@@ -114,7 +120,7 @@ signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_check_code_viol_p, s_serial_input
Check_code_violations: process(uclk_i) Check_code_violations: process(uclk_i)
begin begin
if rising_edge (uclk_i) then if rising_edge (uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_check_code_viol_p <='0'; s_check_code_viol_p <='0';
s_sample_bit_p_d1 <='0'; s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0'; s_sample_bit_p_d2 <='0';
......
wf_model_constr_decoder.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_model_constr_decoder.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_model_constr_decoder.vhd |
---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -12,13 +20,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,13 +20,11 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_model_constr_decoder -- -- WF_model_constr_decoder --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_model_constr_decoder -- unit name WF_model_constr_decoder
-- --
-- --
--! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. --! @brief Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID.
...@@ -44,7 +50,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -44,7 +50,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details\n --! @details\n
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_reset_unit\n --! WF_reset_unit\n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -74,9 +80,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -74,9 +80,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_model_constr_decoder --! Entity declaration for WF_model_constr_decoder
--================================================================================================= --=================================================================================================
entity wf_model_constr_decoder is entity WF_model_constr_decoder is
generic (C_RELOAD_MID_CID : natural); --! reloading of model & constructor generic (C_RELOAD_MID_CID : natural); --! reloading of model & constructor
--! every 2^(C_RELOAD_MID_CID) uclk ticks --! every 2^(C_RELOAD_MID_CID) uclk ticks
port ( port (
...@@ -84,8 +90,8 @@ entity wf_model_constr_decoder is ...@@ -84,8 +90,8 @@ entity wf_model_constr_decoder is
-- User Interface general signal -- User Interface general signal
uclk_i : in std_logic; --! 40 Mhz clock uclk_i : in std_logic; --! 40 Mhz clock
-- Signal from the wf_reset_unit -- Signal from the WF_reset_unit
nFIP_u_rst_i : in std_logic; --! nanoFIP internal reset nFIP_urst_i : in std_logic; --! nanoFIP internal reset
-- WorldFIP settings -- WorldFIP settings
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
...@@ -96,12 +102,12 @@ entity wf_model_constr_decoder is ...@@ -96,12 +102,12 @@ entity wf_model_constr_decoder is
-- WorldFIP settings nanoFIP output -- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector (1 downto 0); --! Identification selection s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to wf_prod_bytes_to_tx -- Output to WF_prod_bytes_to_tx
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
); );
end entity wf_model_constr_decoder; end entity WF_model_constr_decoder;
...@@ -109,7 +115,7 @@ end entity wf_model_constr_decoder; ...@@ -109,7 +115,7 @@ end entity wf_model_constr_decoder;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_model_constr_decoder is architecture rtl of WF_model_constr_decoder is
signal s_load_model_constr_p : std_logic; signal s_load_model_constr_p : std_logic;
...@@ -138,7 +144,7 @@ begin ...@@ -138,7 +144,7 @@ begin
Model_Constructor_Decoder: process(uclk_i) Model_Constructor_Decoder: process(uclk_i)
begin begin
if rising_edge(uclk_i) then -- initializations if rising_edge(uclk_i) then -- initializations
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_counter <= (others => '0'); s_counter <= (others => '0');
m_id_dec_o <= (others => '0'); m_id_dec_o <= (others => '0');
c_id_dec_o <= (others => '0'); c_id_dec_o <= (others => '0');
......
wf_package.vhd
View file @ afec7029
This diff is collapsed.
wf_prod_bytes_to_tx.vhd
View file @ afec7029
This diff is collapsed.
wf_prod_data_lgth_calc.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_prod_data_lgth_calc.vhd --! @file WF_prod_data_lgth_calc.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_prod_data_lgth_calc -- -- WF_prod_data_lgth_calc --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -57,32 +57,32 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -57,32 +57,32 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_prod_data_lgth_calc --! Entity declaration for WF_prod_data_lgth_calc
--================================================================================================= --=================================================================================================
entity wf_prod_data_lgth_calc is entity WF_prod_data_lgth_calc is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
slone_i : in std_logic; slone_i : in std_logic;
nostat_i : in std_logic; nostat_i : in std_logic;
p3_lgth_i : in std_logic_vector (2 downto 0); p3_lgth_i : in std_logic_vector (2 downto 0);
-- Signals from wf_engine_control -- Signals from WF_engine_control
var_i: in t_var; var_i: in t_var;
-- OUTPUT -- OUTPUT
-- Signal to wf_engine_control -- Signal to WF_engine_control
tx_data_length_o : out std_logic_vector(7 downto 0) tx_data_length_o : out std_logic_vector(7 downto 0)
); );
end entity wf_prod_data_lgth_calc; end entity WF_prod_data_lgth_calc;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_prod_data_lgth_calc is architecture rtl of WF_prod_data_lgth_calc is
signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0); signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--================================================================================================= --=================================================================================================
...@@ -93,7 +93,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0); ...@@ -93,7 +93,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
--!@brief:Combinatorial process data_length_calcul: calculation of the total amount of data --!@brief:Combinatorial process data_length_calcul: calculation of the total amount of data
--! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as --! bytes that have to be transferreed when a variable is produced, including the rp_dat.Control as
--! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of the presence --! well as the rp_dat.Data.mps and rp_dat.Data.nanoFIPstatus bytes. In the case of the presence
--! and the identification variables, the data length is predefined in the wf_package. --! and the identification variables, the data length is predefined in the WF_package.
--! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation. --! In the case of a var_3 the inputs slone, nostat and p3_lgth[] are accounted for the calculation.
data_length_calcul: process ( var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i ) data_length_calcul: process ( var_i, s_p3_length_decoded, slone_i, nostat_i, p3_lgth_i )
...@@ -106,15 +106,15 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0); ...@@ -106,15 +106,15 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when presence_var => when var_presence =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package) -- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_PRESENCE_VAR_INDEX).array_length; s_tx_data_length <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
when identif_var => when var_identif =>
-- data length information retreival from the c_VARS_ARRAY matrix (wf_package) -- data length information retreival from the c_VARS_ARRAY matrix (WF_package)
s_tx_data_length <= c_VARS_ARRAY(c_IDENTIF_VAR_INDEX).array_length; s_tx_data_length <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_length;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
...@@ -160,7 +160,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0); ...@@ -160,7 +160,7 @@ signal s_tx_data_length, s_p3_length_decoded : unsigned(7 downto 0);
when var_2 => when var_2 =>
s_tx_data_length <= (others => '0'); s_tx_data_length <= (others => '0');
when reset_var => when var_rst =>
s_tx_data_length <= (others => '0'); s_tx_data_length <= (others => '0');
when others => when others =>
......
wf_reset_unit.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_reset_unit.vhd --! @file WF_reset_unit.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_reset_unit -- -- WF_reset_unit --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name: wf_reset_unit -- unit name: WF_reset_unit
-- --
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset --! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON) --! and user interface reset (RSTON)
...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details --! @details
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_cons_bytes_from_rx\n --! WF_cons_bytes_from_rx\n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -64,49 +64,45 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -64,49 +64,45 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_reset_unit --! Entity declaration for WF_reset_unit
--================================================================================================= --=================================================================================================
entity wf_reset_unit is entity WF_reset_unit is
generic (C_RSTIN_C_LGTH : integer := 3); --! rstin counter length
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized) (after synchronization)
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
rsti_i : in std_logic; --! initialisation control, active low urst_i : in std_logic; --! initialisation control, active low
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding urst_r_edge_i : in std_logic;
subs_i : in std_logic_vector (7 downto 0); --! Subscriber number coding
rate_i : in std_logic_vector (1 downto 0);
-- Signal from the central control unit wf_engine_control -- Signal from the central control unit WF_engine_control
var_i : in t_var; --! variable type var_i : in t_var; --! variable type
rst_nFIP_and_FD_p_i : in std_logic;
-- Signals from the wf_cons_bytes_from_rx unit assert_RSTON_p_i : in std_logic;
rst_var_byte_1_i : in std_logic_vector (7 downto 0);
rst_var_byte_2_i : in std_logic_vector (7 downto 0);
-- OUTPUTS -- OUTPUTS
-- nanoFIP internal reset -- nanoFIP internal reset
nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high nFIP_rst_o : out std_logic; --! nanoFIP internal reset, active high
-- nanoFIP output to the User Interface -- nanoFIP output to the User Interface
rston_o : out std_logic; --! reset output, active low rston_o : out std_logic; --! reset output, active low
-- nanoFIP output to FIELDRIVE -- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
); );
end entity wf_reset_unit; end entity WF_reset_unit;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_reset_unit is architecture rtl of WF_reset_unit is
signal s_rst, s_reset_nFIP_and_FD, s_reset_RSTON : std_logic; signal s_rst : std_logic;
signal s_rstin_c : unsigned(C_RSTIN_C_LGTH downto 0) signal s_rstin_c : unsigned(4 downto 0) := (others=>'0');
:= (others=>'0'); -- init for simulation -- counter init for simulation purpuses
--================================================================================================= --=================================================================================================
...@@ -115,27 +111,27 @@ architecture rtl of wf_reset_unit is ...@@ -115,27 +111,27 @@ architecture rtl of wf_reset_unit is
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process s_rst_creation: the process follows the input signal rstin --!@brief Synchronous process s_rst_creation: the process follows the (buffered) input signal rstin
--! and confirms that it stays active for more than 2^(C_RSTIN_C_LGTH-1) uclk cycles; --! and confirms that it stays active for more than 16 uclk cycles;
--! If so, it enables the signal s_rst to follow it. --! if so, it enables the signal s_rst to follow it.
s_rst_creation: process (uclk_i) s_rst_creation: process (uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if (rsti_i = '1') then -- when the rstin in ON if (urst_i = '1') then -- when the rstin in ON
if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 2^(C_RSTIN_C_LGTH-1) if (s_rstin_c(s_rstin_c'left) = '0') then -- counter counts until 16 (then stays at 16)
s_rstin_c <= s_rstin_c+1; -- then stays at 2^(C_RSTIN_C_LGTH-1) s_rstin_c <= s_rstin_c+1;
end if; end if;
else -- when the reset is OFF else -- when the reset is OFF
s_rstin_c <= (others => '0'); -- counter reinitialized s_rstin_c <= (others => '0'); -- counter reinitialised
end if; end if;
------------------------------------------------- -------------------------------------------------
if (s_rstin_c(s_rstin_c'left) = '1') then -- if rstin was ON for > 2^(C_RSTIN_C_LGTH-1) if (s_rstin_c(s_rstin_c'left) = '1') then -- if rstin was ON for at least 16 uclk ticks
s_rst <= rsti_i; -- uclk ticks, the s_rst starts following rstin s_rst <= urst_i; -- the signal s_rst starts following rstin
else else
s_rst <= '0'; -- otherwise it stays to 0 s_rst <= '0'; -- otherwise it stays to 0
...@@ -147,42 +143,6 @@ end process; ...@@ -147,42 +143,6 @@ end process;
---------------------------------------------------------------------------------------------------
--!@ brief: Generation of the signals s_reset_nFIP_and_FD: signals that the 1st byte of a consumed
--! reset var contains the station address
--! and s_reset_RSTON: signals that the 2nd byte of a consumed
--! reset var contains the station address
Reset_Signals: process (uclk_i)
begin
if rising_edge(uclk_i) then
if s_rst = '1' then
s_reset_nFIP_and_FD <= '0';
s_reset_RSTON <= '0';
else
if var_i = reset_var then
if rst_var_byte_1_i = subs_i then
s_reset_nFIP_and_FD <= '1'; -- reset_nFIP_and_FD_o stays asserted until
end if; -- the end of the current rp_dat frame
if rst_var_byte_2_i = subs_i then
s_reset_RSTON <= '1'; -- reset_RSTON_o stays asserted until
end if; -- the end of the current rp_dat frame
else
s_reset_nFIP_and_FD <= '0';
s_reset_RSTON <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Synchronous process Reset_Outputs: definitions of the three reset outputs: --!@brief Synchronous process Reset_Outputs: definitions of the three reset outputs:
--! rston_o: user interface reset, active low; active when a reset variable is received and the 2nd --! rston_o: user interface reset, active low; active when a reset variable is received and the 2nd
...@@ -201,15 +161,16 @@ end process; ...@@ -201,15 +161,16 @@ end process;
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
rston_o <= not s_reset_RSTON; rston_o <= not assert_RSTON_p_i;
nFIP_rst_o <= s_rst or s_reset_nFIP_and_FD; nFIP_rst_o <= s_rst or rst_nFIP_and_FD_p_i;
fd_rstn_o <= not (s_rst or s_reset_nFIP_and_FD); fd_rstn_o <= not (s_rst or rst_nFIP_and_FD_p_i);
end if; end if;
end process; end process;
end architecture rtl; end architecture rtl;
--================================================================================================= --=================================================================================================
-- architecture end -- architecture end
--================================================================================================= --=================================================================================================
......
wf_rx.vhd
View file @ afec7029
This diff is collapsed.
wf_rx_deglitcher.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_rx_deglitcher.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_rx_deglitcher.vhd |
---------------------------------------------------------------------------------------------------
--! Standard library --! Standard library
library IEEE; library IEEE;
...@@ -12,9 +20,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,9 +20,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_rx_deglitcher -- -- WF_rx_deglitcher --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -24,7 +30,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -24,7 +30,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
-- --
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- --
-- @date 08/2010 -- @date 08/2010
...@@ -36,8 +42,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -36,8 +42,8 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! @details --! @details
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_osc \n --! WF_osc \n
--! wf_reset_unit \n --! WF_reset_unit \n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -59,10 +65,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -59,10 +65,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_deglitcher --! Entity declaration for WF_deglitcher
--================================================================================================= --=================================================================================================
entity wf_rx_deglitcher is entity WF_rx_deglitcher is
generic (C_ACULENGTH : integer := 10); generic (C_ACULENGTH : integer := 10);
port( port(
...@@ -70,31 +76,31 @@ entity wf_rx_deglitcher is ...@@ -70,31 +76,31 @@ entity wf_rx_deglitcher is
-- User interface general signal -- User interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- FIELDRIVE input signal -- FIELDRIVE input signal
rxd_i : in std_logic; --! buffered fd_rxd rxd_i : in std_logic; --! buffered fd_rxd
-- Signals from the wf_osc unit -- Signals from the WF_osc unit
sample_bit_p_i : in std_logic; --! pulsed signal signaling a new bit sample_bit_p_i : in std_logic; --! pulsed signal signaling a new bit
sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit
-- OUTPUTS -- OUTPUTS
-- Output signals needed for the receiverwf_rx -- Output signals needed for the receiverWF_rx
sample_bit_p_o : out std_logic; sample_bit_p_o : out std_logic;
rxd_filtered_o : out std_logic; rxd_filtered_o : out std_logic;
rxd_filtered_f_edge_p_o : out std_logic; rxd_filtered_f_edge_p_o : out std_logic;
sample_manch_bit_p_o : out std_logic sample_manch_bit_p_o : out std_logic
); );
end wf_rx_deglitcher; end WF_rx_deglitcher;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture Behavioral of wf_rx_deglitcher is architecture Behavioral of WF_rx_deglitcher is
signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0); signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rxd_filtered : std_logic; signal s_rxd_filtered : std_logic;
...@@ -114,7 +120,7 @@ process(uclk_i) ...@@ -114,7 +120,7 @@ process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_count_ones_c <= (others =>'0'); s_count_ones_c <= (others =>'0');
else else
...@@ -136,7 +142,7 @@ process(uclk_i) ...@@ -136,7 +142,7 @@ process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_rxd_filtered <= '0'; s_rxd_filtered <= '0';
s_rxd_filtered_d <= '0'; s_rxd_filtered_d <= '0';
else else
...@@ -162,7 +168,7 @@ end process; ...@@ -162,7 +168,7 @@ end process;
Detect_f_edge_rx_data_filtered: process(uclk_i) Detect_f_edge_rx_data_filtered: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_rxd_filtered_buff <= (others => '0'); s_rxd_filtered_buff <= (others => '0');
rxd_filtered_f_edge_p_o <= '0'; rxd_filtered_f_edge_p_o <= '0';
else else
...@@ -190,32 +196,3 @@ end Behavioral; ...@@ -190,32 +196,3 @@ end Behavioral;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
wf_rx_tx_osc.vhd
View file @ afec7029
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wf_slone_DATI_bytes_sampler.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_slone_DATI_bytes_sampler.vhd --! @file WF_slone_DATI_bytes_sampler.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,7 +14,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_slone_DATI_bytes_sampler -- -- WF_slone_DATI_bytes_sampler --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -57,40 +57,40 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -57,40 +57,40 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_slone_DATI_bytes_sampler --! Entity declaration for WF_slone_DATI_bytes_sampler
--================================================================================================= --=================================================================================================
entity wf_slone_DATI_bytes_sampler is entity WF_slone_DATI_bytes_sampler is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- User Interface Non WISHBONE -- User Interface Non WISHBONE
slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode slone_data_i : in std_logic_vector (15 downto 0);--! input data bus for slone mode
-- (triply buffered with uclk) -- (triply buffered with uclk)
-- Signals from wf_engine_control -- Signals from WF_engine_control
var3_rdy_i : in std_logic; var3_rdy_i : in std_logic;
byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes byte_index_i : in std_logic_vector (7 downto 0); --! pointer to message bytes
-- includes rp_dat.Control and rp_dat.Data -- includes rp_dat.Control and rp_dat.Data
-- OUTPUTS -- OUTPUTS
-- Signal to wf_prod_bytes_to_tx -- Signal to WF_prod_bytes_to_tx
slone_byte_o : out std_logic_vector (7 downto 0) slone_byte_o : out std_logic_vector (7 downto 0)
); );
end entity wf_slone_DATI_bytes_sampler; end entity WF_slone_DATI_bytes_sampler;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_slone_DATI_bytes_sampler is architecture rtl of WF_slone_DATI_bytes_sampler is
signal s_var3_rdy_d4 : std_logic_vector (3 downto 0); signal s_var3_rdy_d4 : std_logic_vector (3 downto 0);
signal s_sampled_data : std_logic_vector (15 downto 0); signal s_sampled_data : std_logic_vector (15 downto 0);
...@@ -109,7 +109,7 @@ architecture rtl of wf_slone_DATI_bytes_sampler is ...@@ -109,7 +109,7 @@ architecture rtl of wf_slone_DATI_bytes_sampler is
Sample_Data_i: process(uclk_i) Sample_Data_i: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
s_var3_rdy_d4 <= (others=>'0'); s_var3_rdy_d4 <= (others=>'0');
s_sampled_data <= (others=>'0'); s_sampled_data <= (others=>'0');
else else
......
wf_slone_bytes_to_DATO.vhd
View file @ afec7029
--================================================================================================= --________________________________________________________________________________________________|
--! @file wf_slone_bytes_to_DATO.vhd -- |
--================================================================================================= -- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
--! @file WF_slone_bytes_to_DATO.vhd |
---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,9 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,9 +22,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_slone_bytes_to_DATO -- -- WF_slone_bytes_to_DATO --
-- --
-- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -59,40 +65,38 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -59,40 +65,38 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_slone_bytes_to_DATO --! Entity declaration for WF_slone_bytes_to_DATO
--================================================================================================= --=================================================================================================
entity wf_slone_bytes_to_DATO is entity WF_slone_bytes_to_DATO is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the wf_reset_unit unit -- Signal from the WF_reset_unit unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from wf_cons_bytes_from_rx -- Signals from WF_cons_bytes_from_rx
transfer_byte_p_i: in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_o(7:0) transfer_byte_p_i: in std_logic_vector (1 downto 0); --! 01: byte_i transfered to DAT_o(7:0)
--! 10: byte_i transfered to DAT_o(15:8) --! 10: byte_i transfered to DAT_o(15:8)
-- Signals for the receiver wf_rx -- Signals for the receiver WF_rx
byte_i : in std_logic_vector (7 downto 0); --! byte received from the rx unit byte_i : in std_logic_vector (7 downto 0); --! byte received from the rx unit
-- OUTPUTS -- OUTPUTS
-- Signal to wf_prod_bytes_to_tx -- Signal to WF_prod_bytes_to_tx
slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O slone_data_o : out std_logic_vector (15 downto 0) --! output bus DAT_O
); );
end entity wf_slone_bytes_to_DATO; end entity WF_slone_bytes_to_DATO;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_slone_bytes_to_DATO is architecture rtl of WF_slone_bytes_to_DATO is
--================================================================================================= --=================================================================================================
...@@ -109,7 +113,7 @@ architecture rtl of wf_slone_bytes_to_DATO is ...@@ -109,7 +113,7 @@ architecture rtl of wf_slone_bytes_to_DATO is
Data_Transfer_To_Dat_o: process (uclk_i) Data_Transfer_To_Dat_o: process (uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' then if nFIP_urst_i = '1' then
slone_data_o <= (others => '0'); -- bus initialization slone_data_o <= (others => '0'); -- bus initialization
else else
......
wf_status_bytes_gen.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_status_bytes_gen.vhd --! @file WF_status_bytes_gen.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_status_bytes_generator -- -- WF_status_bytes_generator --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_status_bytes_gen -- unit name WF_status_bytes_gen
-- --
-- --
--! @brief Generation of the NanoFIP status, as well as the MPS status bytes. --! @brief Generation of the NanoFIP status, as well as the MPS status bytes.
...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! data_if \n --! data_if \n
--! tx_engine \n --! tx_engine \n
--! wf_tx_rx \n --! WF_tx_rx \n
--! reset_logic \n --! reset_logic \n
-- --
-- --
...@@ -65,18 +65,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -65,18 +65,18 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
-- Entity declaration for wf_status_bytes_gen -- Entity declaration for WF_status_bytes_gen
--================================================================================================= --=================================================================================================
entity wf_status_bytes_gen is entity WF_status_bytes_gen is
port ( port (
-- INPUTS -- INPUTS
-- User Interface general signals -- User Interface general signals (synchronized)
uclk_i : in std_logic; --! 40 MHz Clock uclk_i : in std_logic; --! 40 MHz Clock
slone_i : in std_logic; --! Stand-alone mode slone_i : in std_logic; --! Stand-alone mode
-- Signal from the reset_logic unit -- Signal from the reset_logic unit
nFIP_u_rst_i : in std_logic; --! internal reset nFIP_urst_i : in std_logic; --! internal reset
-- Signals from the fieldrive interface -- Signals from the fieldrive interface
fd_wdgn_i : in std_logic; --! Watchdog on transmitter fd_wdgn_i : in std_logic; --! Watchdog on transmitter
...@@ -87,10 +87,10 @@ port ( ...@@ -87,10 +87,10 @@ port (
var2_acc_i : in std_logic; --! Variable 2 access (asynchronous) var2_acc_i : in std_logic; --! Variable 2 access (asynchronous)
var3_acc_i : in std_logic; --! Variable 3 access (asynchronous) var3_acc_i : in std_logic; --! Variable 3 access (asynchronous)
-- Signal from the receiver wf_rx -- Signal from the receiver WF_rx
crc_wrong_p_i : in std_logic; crc_wrong_p_i : in std_logic;
-- Signals from the central control unit wf_engine_control -- Signals from the central control unit WF_engine_control
var_i : in t_var; --! variable type var_i : in t_var; --! variable type
var1_rdy_i : in std_logic; --! Variable 1 ready var1_rdy_i : in std_logic; --! Variable 1 ready
var2_rdy_i : in std_logic; --! Variable 2 ready var2_rdy_i : in std_logic; --! Variable 2 ready
...@@ -98,20 +98,20 @@ port ( ...@@ -98,20 +98,20 @@ port (
-- Signal from nanofip -- Signal from nanofip
reset_status_bytes_i : in std_logic; --! both status bytes are reinitialized rst_status_bytes_i : in std_logic; --! both status bytes are reinitialized
--! right after having been delivered --! right after having been delivered
-- OUTPUTS -- OUTPUTS
-- Output to wf_prod_bytes_to_tx -- Output to WF_prod_bytes_to_tx
nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! status byte nFIP_status_byte_o : out std_logic_vector (7 downto 0); --! status byte
mps_status_byte_o : out std_logic_vector (7 downto 0) --! mps byte mps_status_byte_o : out std_logic_vector (7 downto 0) --! mps byte
); );
end entity wf_status_bytes_gen; end entity WF_status_bytes_gen;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_status_bytes_gen is architecture rtl of WF_status_bytes_gen is
signal s_refreshment : std_logic; signal s_refreshment : std_logic;
...@@ -131,7 +131,7 @@ begin ...@@ -131,7 +131,7 @@ begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if ((nFIP_u_rst_i = '1') or (reset_status_bytes_i = '1')) then -- the byte is reinitialized if ((nFIP_urst_i = '1') or (rst_status_bytes_i = '1')) then -- the byte is reinitialized
nFIP_status_byte_o <= (others => '0'); -- after having been delivered nFIP_status_byte_o <= (others => '0'); -- after having been delivered
else else
...@@ -182,7 +182,7 @@ end process; ...@@ -182,7 +182,7 @@ end process;
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_u_rst_i = '1' or reset_status_bytes_i = '1' then -- the bit is reinitialized if nFIP_urst_i = '1' or rst_status_bytes_i = '1' then -- the bit is reinitialized
s_refreshment <= '0'; -- after having been delivered s_refreshment <= '0'; -- after having been delivered
else else
......
wf_tx.vhd
View file @ afec7029
This diff is collapsed.
wf_tx_rx.vhd
View file @ afec7029
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! @file wf_tx_rx.vhd --! @file WF_tx_rx.vhd
--================================================================================================= ---------------------------------------------------------------------------------------------------
--! standard library --! standard library
library IEEE; library IEEE;
...@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -14,13 +14,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_tx_rx -- -- WF_tx_rx --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name: wf_tx_rx -- unit name: WF_tx_rx
-- --
--! @brief Serializes and deserializes the WorldFIP data. --! @brief Serializes and deserializes the WorldFIP data.
--! --!
...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! On reception it depacketises the data and only presents the actual data --! On reception it depacketises the data and only presents the actual data
--! contents. It also verifies the FCS (Frame Checksum, CRC).\n --! contents. It also verifies the FCS (Frame Checksum, CRC).\n
--! On transmission it packetises the data and adds the FCS. --! On transmission it packetises the data and adds the FCS.
--! The unit wf_rx_tx_osc recovers the carrier clock during --! The unit WF_rx_tx_osc recovers the carrier clock during
--! --!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- --
...@@ -39,10 +39,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -39,10 +39,10 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! @details --! @details
--! --!
--! <b>Dependencies:</b>\n --! <b>Dependencies:</b>\n
--! wf_engine \n --! WF_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! wf_reset_unit \n --! WF_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
--! --!
--! --!
...@@ -64,14 +64,14 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -64,14 +64,14 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_tx_rx --! Entity declaration for WF_tx_rx
--================================================================================================= --=================================================================================================
entity wf_tx_rx is entity WF_tx_rx is
port ( port (
uclk_i : in std_logic; --! User Clock uclk_i : in std_logic; --! User Clock
nFIP_u_rst_i : in std_logic; nFIP_urst_i : in std_logic;
reset_rx_unit_p_i : in std_logic; rst_rx_unit_p_i : in std_logic;
start_produce_p_i : in std_logic; start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic; byte_ready_p_i : in std_logic;
byte_i : in std_logic_vector (7 downto 0); byte_i : in std_logic_vector (7 downto 0);
...@@ -92,14 +92,14 @@ entity wf_tx_rx is ...@@ -92,14 +92,14 @@ entity wf_tx_rx is
FSS_CRC_FES_viol_ok_p_o : out std_logic FSS_CRC_FES_viol_ok_p_o : out std_logic
); );
end entity wf_tx_rx; end entity WF_tx_rx;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_tx_rx is architecture rtl of WF_tx_rx is
signal s_d_filtered, s_first_fe : std_logic; signal s_d_filtered, s_first_fe : std_logic;
signal s_rx_data_filtered_f_edge_p : std_logic; signal s_rx_data_filtered_f_edge_p : std_logic;
...@@ -114,11 +114,11 @@ architecture rtl of wf_tx_rx is ...@@ -114,11 +114,11 @@ architecture rtl of wf_tx_rx is
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
tx: wf_tx tx: WF_tx
generic map(C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH) generic map(C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH)
PORT MAP( PORT MAP(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i, nFIP_urst_i => nFIP_urst_i,
start_produce_p_i => start_produce_p_i, start_produce_p_i => start_produce_p_i,
byte_ready_p_i => byte_ready_p_i, byte_ready_p_i => byte_ready_p_i,
byte_i => byte_i, byte_i => byte_i,
...@@ -130,11 +130,11 @@ begin ...@@ -130,11 +130,11 @@ begin
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
rx: wf_rx rx: WF_rx
PORT MAP( PORT MAP(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i, nFIP_urst_i => nFIP_urst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i, rst_rx_unit_p_i => rst_rx_unit_p_i,
sample_bit_p_i => s_sample_bit_p, sample_bit_p_i => s_sample_bit_p,
signif_edge_window_i => s_signif_edge_window, signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window, adjac_bits_window_i => s_adjac_bits_window,
...@@ -146,25 +146,25 @@ begin ...@@ -146,25 +146,25 @@ begin
byte_ready_p_o => byte_ready_p_o, byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o, byte_o => byte_o,
FSS_CRC_FES_viol_ok_p_o => FSS_CRC_FES_viol_ok_p_o, FSS_CRC_FES_viol_ok_p_o => FSS_CRC_FES_viol_ok_p_o,
wait_rxd_first_f_edge_o => s_first_fe, rst_rx_osc_o => s_first_fe,
FSS_received_p_o => FSS_received_p_o, FSS_received_p_o => FSS_received_p_o,
CRC_wrong_p_o => CRC_wrong_p_o CRC_wrong_p_o => CRC_wrong_p_o
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
rx_tx_osc :wf_rx_tx_osc rx_tx_osc :WF_rx_tx_osc
generic map(C_PERIODS_COUNTER_LENGTH => C_PERIODS_COUNTER_LENGTH, generic map(C_PERIODS_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => C_QUARTZ_PERIOD, C_QUARTZ_PERIOD => 24.8,
C_TXCLKBUFFLENTGTH => C_TXCLKBUFFLENTGTH) C_TXCLKBUFFLENTGTH => 4)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i, nFIP_urst_i => nFIP_urst_i,
rxd_edge_i => fd_rxd_edge_i, rxd_edge_i => fd_rxd_edge_i,
rxd_f_edge_i => fd_rxd_f_edge_i, rxd_f_edge_i => fd_rxd_f_edge_i,
wait_rxd_first_f_edge_i => s_first_fe, rst_rx_osc_i => s_first_fe,
rate_i => rate_i, rate_i => rate_i,
tx_clk_p_buff_o => s_clk_fixed_carrier_p_d, tx_clk_p_buff_o => s_clk_fixed_carrier_p_d,
tx_clk_o => d_clk_o, tx_clk_o => d_clk_o,
...@@ -175,10 +175,10 @@ begin ...@@ -175,10 +175,10 @@ begin
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
deglitcher : wf_rx_deglitcher deglitcher : WF_rx_deglitcher
generic map (C_ACULENGTH => 10) generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i, Port map( uclk_i => uclk_i,
nFIP_u_rst_i => nFIP_u_rst_i, nFIP_urst_i => nFIP_urst_i,
rxd_i => fd_rxd, rxd_i => fd_rxd,
sample_bit_p_i => s_rx_bit_clk_p, sample_bit_p_i => s_rx_bit_clk_p,
sample_manch_bit_p_i => s_rx_manch_clk_p, sample_manch_bit_p_i => s_rx_manch_clk_p,
......
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