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urv-core
Commit e5f1afaf authored by Tristan Gingold's avatar Tristan Gingold
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Set r0 to 0 during reset (for flash FPGAs).

parent 193f15db
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Showing with 10 additions and 5 deletions
rtl/urv_exec.v
View file @ e5f1afaf
......@@ -503,7 +503,12 @@ module urv_exec
f_dbg_toggle_o <= 0;
w_load_o <= 0;
w_store_o <= 0;
w_valid_o <= 0;
// Values so that 0 could be written to register 0.
w_rd_value_o <= 0;
w_rd_o <= 0;
w_rd_source_o <= `RD_SOURCE_ALU;
w_rd_write_o <= 1;
w_valid_o <= 1;
end
else
begin
......
rtl/urv_regfile.v
View file @ e5f1afaf
......@@ -31,7 +31,6 @@
module urv_regmem
(
input clk_i,
input rst_i,
input en1_i,
input [4:0] a1_i,
......@@ -92,12 +91,14 @@ module urv_regfile
wire [31:0] rs1_regfile;
wire [31:0] rs2_regfile;
wire write = (w_rd_store_i && (w_rd_i != 0));
// By adding rst_i, register 0 is written (to 0) during reset. This is
// required on some flash FPGA (like smartfusion2 or ProASIC3) which
// doesn't support initialized RAMs.
wire write = rst_i || (w_rd_store_i && (w_rd_i != 0));
urv_regmem bank0
(
.clk_i(clk_i),
.rst_i (rst_i ),
.en1_i(!d_stall_i),
.a1_i(rf_rs1_i),
.q1_o(rs1_regfile),
......@@ -110,7 +111,6 @@ module urv_regfile
urv_regmem bank1
(
.clk_i(clk_i),
.rst_i (rst_i ),
.en1_i(!d_stall_i),
.a1_i(rf_rs2_i),
.q1_o(rs2_regfile),
......
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