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VME SBC A25 PCIe to VME bridge
Commit d067b548 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '16-hdl-simplify-address-decoder-from-pcie' into 'master' 

Resolve "HDL: simplify address decoder from PCIe"

Closes #16

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!12
parents 877f35ee 8c05fdfa
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Showing with 83 additions and 524 deletions
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @ d067b548
......@@ -49,7 +49,6 @@ use work.fpga_pkg_2.all;
entity ip_16z091_01 is
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2; -- only specify values between 0 and 2
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001"; -- = 1017 DW;
-- set this value to "1111111111" - (READY_LATENCY + 1)
......@@ -120,15 +119,13 @@ entity ip_16z091_01 is
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_cyc_bar_o : out std_logic_vector(6 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
......@@ -286,7 +283,6 @@ begin
wb_master_comp : entity work.z091_01_wb_master
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
SUSPEND_FIFO_ACCESS => WBM_SUSPEND_FIFO_ACCESS,
RESUME_FIFO_ACCESS => WBM_RESUME_FIFO_ACCESS
)
......@@ -314,15 +310,13 @@ begin
wbm_ack => wbm_ack,
wbm_dat_i => wbm_dat_i,
wbm_stb => wbm_stb,
--wbm_cyc => wbm_cyc,
wbm_cyc_o => wbm_cyc_o,
wbm_cyc_bar_o => wbm_cyc_bar_o,
wbm_we => wbm_we,
wbm_sel => wbm_sel,
wbm_adr => wbm_adr,
wbm_dat_o => wbm_dat_o,
wbm_cti => wbm_cti,
wbm_tga => wbm_tga,
--wb_bar_dec => wb_bar_dec,
-- error
ecrc_err_in => ecrc_err_wb_int,
......
hdl/16z091-01_src/Source/z091_01_wb_master.vhd
View file @ d067b548
......@@ -53,7 +53,6 @@ use work.src_utils_pkg.all;
entity z091_01_wb_master is
generic(
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011"; -- = 1019 DW
RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111" -- = 1015 DW
);
......@@ -81,15 +80,13 @@ entity z091_01_wb_master is
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_cyc_bar_o : out std_logic_vector(6 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic; -- wbm_tga(0)=1 if ECRC error occured
--wb_bar_dec : out std_logic_vector(6 downto 0); -- decoded BAR for wb_adr_dec.vhd mwawrik: no longer necessary
-- error
ecrc_err_in : in std_logic; -- input from error module
......@@ -151,25 +148,10 @@ signal wb_bar_dec_int_d : std_logic_vector(6 downto 0);
signal ecrc_err_int : std_logic;
signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
-------------------------------------------------------------------------------
begin
z091_01_wb_adr_dec_comp : entity work.z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
port map(
pci_cyc_i => wb_bar_dec_int,
wbm_adr_o_q => addr_int(31 downto 2),
wbm_cyc_o => wbm_cyc_o_int
);
wb_bar_dec_int <= bar_dec_int when (state = START_TRANS) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B
and tx_fifo_c_data_full = '0' and goto_start = '0') else
......@@ -179,8 +161,6 @@ begin
else
wb_bar_dec_int_d;
--wb_bar_dec <= wb_bar_dec_int_d; --mwawrik: no longer necessary because out-pin wb_bar_dec removed
ecrc_err_int <= '0' when wb_rst = '1' else
'0' when state = TRANSMIT else
'1' when state /= TRANSMIT and ecrc_err_in = '1';
......@@ -309,7 +289,7 @@ begin
tx_fifo_c_data_clr <= '1';
tx_fifo_c_head_clr <= '1';
wbm_stb <= '0';
wbm_cyc_o <= (others => '0');
wbm_cyc_bar_o <= (others => '0');
wbm_we <= '0';
wbm_sel <= (others => '0');
wbm_adr <= (others => '0');
......@@ -438,17 +418,17 @@ begin
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb > ZERO_11B) ) then
wbm_cti <= "010";
wbm_cyc_o <= wbm_cyc_o_int;
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif((state = START_TRANS and suspend = '0' and length_int = ONE_10B) or
(state = TRANSMIT and wbm_ack = '1' and (cnt_len_wb = ONE_11B or (tx_fifo_c_data_usedw = SUSPEND_FIFO_ACCESS and
wr_en_int = '0'))) or
(state = WAIT_ON_FIFO and tx_fifo_c_data_usedw <= RESUME_FIFO_ACCESS and tx_fifo_c_data_usedw /= ZERO_10B and
tx_fifo_c_data_full = '0' and goto_start = '0' and cnt_len_wb <= ZERO_11B) ) then
wbm_cti <= "111";
wbm_cyc_o <= wbm_cyc_o_int;
wbm_cyc_bar_o <= wb_bar_dec_int;
elsif(wbm_ack = '1' and cnt_len_wb = ZERO_11B and (state = TRANSMIT or (state = START_TRANS and wr_en_int = '1')) ) then
wbm_cti <= "000";
wbm_cyc_o <= (OTHERS=>'0');
wbm_cyc_bar_o <= (OTHERS=>'0');
end if;
if(state = IDLE or (state = TRANSMIT and wbm_ack = '1' and cnt_len_wb = ZERO_11B)) then
......
hdl/top/A25_top.vhd
View file @ d067b548
......@@ -123,8 +123,6 @@ END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT pll_pcie
PORT
(
......@@ -185,7 +183,7 @@ END COMPONENT;
SIGNAL wbmo_0 : wbo_type;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_int : std_logic_vector(9 DOWNTO 0);
SIGNAL wbmo_0_cyc_bar : std_logic_vector(6 downto 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
......@@ -374,34 +372,80 @@ pll: pll_pcie
locked => pll_locked
);
wbmo_0_cyc <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
"0001" WHEN wbmo_0_cyc_int(0) = '1' ELSE -- | Chameleon Table | 0 | 0 | 200 | 0 |
"0010" WHEN wbmo_0_cyc_int(1) = '1' ELSE -- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
"0100" WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 200 | 0 |
"0100" WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
"0100" WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
"1000" WHEN wbmo_0_cyc_int(5) = '1' ELSE -- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
"0100" WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
"0100" WHEN wbmo_0_cyc_int(8) = '1' ELSE -- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
"0100" WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CR/CSR | 9 | 0 | 01000000 | 4 |
"0000"; -- +--------------------------+-----+----------+----------+-----+
-- +-Module Name--------------+-dst-+---offset-+------size-+-bar-+
-- | Chameleon Table | cam | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | flh | 200 | 20 | 0 |
-- |16z002-01 VME REGS | vme | 10000 | 200 | 0 |
-- |16z002-01 VME IACK | vme | 10200 | 200 | 0 |
-- |16z002-01 VME A16D16 | vme | 20000 | 1_0000 | 0 |
-- |16z002-01 VME A16D32 | vme | 30000 | 1_0000 | 0 |
-- | 16z002-01 VME SRAM | ram | 0 | 10_0000 | 1 |
-- |16z002-01 VME A24D16 | vme | 0 | 100_0000 | 2 |
-- |16z002-01 VME A24D32 | vme | 1000000 | 100_0000 | 2 |
-- | 16z002-01 VME A32 | vme | 0 | 2000_0000 | 3 |
-- |16z002-01 VME CR/CSR | vme | 0 | 100_0000 | 4 |
-- +--------------------------+-----+----------+-----------+-----+
process (wbmo_0_cyc_bar, wbmo_0)
begin
wbmo_0_cyc <= "0000";
wbmo_0.tga(6 DOWNTO 0) <= (others => 'X');
if wbmo_0_cyc_bar(0) = '1' then
case wbmo_0.adr(17 DOWNTO 16) is
when "00" =>
if wbmo_0.adr(15 DOWNTO 9) = "0000000" then
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
wbmo_0_cyc <= "0001";
elsif wbmo_0.adr(15 DOWNTO 5) = "00000010000" then
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
wbmo_0_cyc <= "0010";
end if;
when "01" =>
wbmo_0_cyc <= "0100";
if wbmo_0.adr(8) = '1' then
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_IACK;
else
-- 16z002-01 VME regs - cycle 2 - offset 10000 - size 10000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_REGS;
end if;
when "10" =>
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D16;
when "11" =>
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A16D32;
when others =>
null;
end case;
elsif wbmo_0_cyc_bar (1) = '1' then
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
wbmo_0_cyc <= "1000";
elsif wbmo_0_cyc_bar (2) = '1' then
wbmo_0_cyc <= "0100";
if wbmo_0.adr(24) = '0' then
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D16;
else
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D32;
end if;
elsif wbmo_0_cyc_bar (3) = '1' then
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A32D32;
elsif wbmo_0_cyc_bar (4) = '1' then
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_CRCSR;
end if;
end process;
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
wbmo_0.tga(6 DOWNTO 0) <= -- +-Module Name--------------+-cyc-+---offset-+-----size-+-bar-+
CONST_VME_A24D16 WHEN wbmo_0_cyc_int(6) = '1' ELSE -- |16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
CONST_VME_A16D16 WHEN wbmo_0_cyc_int(3) = '1' ELSE -- |16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
CONST_VME_A16D32 WHEN wbmo_0_cyc_int(4) = '1' ELSE -- |16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
CONST_VME_IACK WHEN wbmo_0_cyc_int(2) = '1'
AND wbmo_0.adr(8) = '1' ELSE -- |16z002-01 VME IACK | 2 | 10100 | 10 | 0 |
CONST_VME_REGS WHEN wbmo_0_cyc_int(2) = '1' ELSE -- |16z002-01 VME REGS | 2 | 10000 | 100 | 0 |
CONST_VME_A32D32 WHEN wbmo_0_cyc_int(8) = '1' ELSE -- |16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
CONST_VME_A24D32 WHEN wbmo_0_cyc_int(7) = '1' ELSE -- |16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: entity work.ip_16z091_01_top
GENERIC MAP (
......@@ -409,20 +453,6 @@ pcie: entity work.ip_16z091_01_top
FPGA_FAMILY => CYCLONE4,
IRQ_WIDTH => 13,
USE_LANES => f_sel_pcie_lanes(SIMULATION),
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
NR_OF_BARS_USED => 5,
VENDOR_ID => 16#1A88#,
DEVICE_ID => 16#4D45#,
REVISION_ID => 16#1#,
CLASS_CODE => 16#068000#,
SUBSYSTEM_VENDOR_ID => 16#D5#,
SUBSYSTEM_DEVICE_ID => 16#5A91#,
BAR_MASK_0 => x"FFFC0000", -- 256k
BAR_MASK_1 => x"FFF00000", -- 1M
BAR_MASK_2 => x"FE000000", -- 32M
BAR_MASK_3 => x"E0000000", -- 512M
BAR_MASK_4 => x"FF000000", -- 16M
BAR_MASK_5 => x"FFFFF000",
PCIE_REQUEST_LENGTH => "0001000000", -- 64DW = 256Byte
RX_LPM_WIDTHU => 10,
TX_HEADER_LPM_WIDTHU => 5,
......@@ -452,7 +482,7 @@ pcie: entity work.ip_16z091_01_top
wbm_ack => wbmi_0.ack,
wbm_dat_i => wbmi_0.dat,
wbm_stb => wbmo_0.stb,
wbm_cyc_o => wbmo_0_cyc_int,
wbm_cyc_bar_o => wbmo_0_cyc_bar,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
......@@ -472,14 +502,7 @@ pcie: entity work.ip_16z091_01_top
wbs_err => open,
wbs_dat_o => wbso_4.dat,
irq_req_i(0) => vme_irq(0),
irq_req_i(1) => vme_irq(1),
irq_req_i(2) => vme_irq(2),
irq_req_i(3) => vme_irq(3),
irq_req_i(4) => vme_irq(4),
irq_req_i(5) => vme_irq(5),
irq_req_i(6) => vme_irq(6),
irq_req_i(7) => vme_irq(7),
irq_req_i(7 downto 0) => vme_irq,
irq_req_i(8) => berr_irq,
irq_req_i(9) => dma_irq,
irq_req_i(10) => locmon_irq(0),
......@@ -493,8 +516,7 @@ pcie: entity work.ip_16z091_01_top
error_r2c0 => open,
error_msi_num => open,
link_train_active => open,
gp_debug_port => open
link_train_active => open
);
......
hdl/top/Manifest.py
View file @ d067b548
......@@ -26,5 +26,4 @@ files = [
"sram.vhd",
"wb_bus.vhd",
"wb_pkg.vhd",
"z091_01_wb_adr_dec.vhd",
]
hdl/top/z091_01_wb_adr_dec.vhd deleted 100644 → 0
View file @ 877f35ee
-- SPDX-FileCopyrightText: 2016, MEN Mikro Elektronik GmbH
-- SPDX-License-Identifier: CERN-OHL-S-2.0+
--------------------------------------------------------------------------------
-- Title : 16z091-01 specific Wishbone bus
-- Project :
-------------------------------------------------------------------------------
-- File : z091_01_wb_adr_dec.vhd
-- Author : Susanne Reinfelder
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 2012-12-19
-------------------------------------------------------------------------------
-- Simulator :
-- Synthesis :
-------------------------------------------------------------------------------
-- +-Module Name-------------------+-cyc-+---offset-+-----size-+-bar-+
-- | Chameleon Table | 0 | 0 | 200 | 0 |
-- | 16Z126_SERFLASH | 1 | 200 | 20 | 0 |
-- | 16z002-01 VME | 2 | 10000 | 10000 | 0 |
-- | 16z002-01 VME A16D16 | 3 | 20000 | 10000 | 0 |
-- | 16z002-01 VME A16D32 | 4 | 30000 | 10000 | 0 |
-- | 16z002-01 VME SRAM | 5 | 0 | 100000 | 1 |
-- | 16z002-01 VME A24D16 | 6 | 0 | 1000000 | 2 |
-- | 16z002-01 VME A24D32 | 7 | 1000000 | 1000000 | 2 |
-- | 16z002-01 VME A32 | 8 | 0 | 20000000 | 3 |
-- +-------------------------------+-----+----------+----------+-----+
--
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
entity z091_01_wb_adr_dec is
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port(
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end z091_01_wb_adr_dec;
-------------------------------------------------------------------------
-- sim_test_arch implements a sample pcie address decoder to enable
-- the simulation iram models
-------------------------------------------------------------------------
architecture a25_arch of z091_01_wb_adr_dec is
begin
PROCESS(wbm_adr_o_q, pci_cyc_i)
VARIABLE wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 DOWNTO 0);
CONSTANT zero : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0):=(OTHERS => '0');
BEGIN
wbm_cyc_o_int := (OTHERS => '0');
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 9) = "000000000" THEN
wbm_cyc_o_int(0) := '1';
ELSE
wbm_cyc_o_int(0) := '0';
END IF;
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 5) = "0000000010000" THEN
wbm_cyc_o_int(1) := '1';
ELSE
wbm_cyc_o_int(1) := '0';
END IF;
-- 16z002-01 VME - cycle 2 - offset 10000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "01" THEN
wbm_cyc_o_int(2) := '1';
ELSE
wbm_cyc_o_int(2) := '0';
END IF;
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "10" THEN
wbm_cyc_o_int(3) := '1';
ELSE
wbm_cyc_o_int(3) := '0';
END IF;
-- 16z002-01 VME A16D32 - cycle 4 - offset 30000 - size 10000 --
IF pci_cyc_i(0) = '1' AND wbm_adr_o_q(17 DOWNTO 16) = "11" THEN
wbm_cyc_o_int(4) := '1';
ELSE
wbm_cyc_o_int(4) := '0';
END IF;
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
IF pci_cyc_i(1) = '1' THEN
wbm_cyc_o_int(5) := '1';
ELSE
wbm_cyc_o_int(5) := '0';
END IF;
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '0' THEN
wbm_cyc_o_int(6) := '1';
ELSE
wbm_cyc_o_int(6) := '0';
END IF;
-- 16z002-01 VME A24D32 - cycle 7 - offset 1000000 - size 1000000 --
IF pci_cyc_i(2) = '1' AND wbm_adr_o_q(24) = '1' THEN
wbm_cyc_o_int(7) := '1';
ELSE
wbm_cyc_o_int(7) := '0';
END IF;
-- 16z002-01 VME A32 - cycle 8 - offset 0 - size 20000000 --
IF pci_cyc_i(3) = '1' THEN
wbm_cyc_o_int(8) := '1';
ELSE
wbm_cyc_o_int(8) := '0';
END IF;
-- 16z002-01 VME CRCSR - cycle 9 - offset 0 - size 1000000 --
IF pci_cyc_i(4) = '1' THEN
wbm_cyc_o_int(9) := '1';
ELSE
wbm_cyc_o_int(9) := '0';
END IF;
IF or_reduce(pci_cyc_i) = '1' AND wbm_cyc_o_int = zero THEN
wbm_cyc_o_int(0) := '1';
END IF;
wbm_cyc_o <= wbm_cyc_o_int;
END PROCESS;
end a25_arch;
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