Skip to content

V
VME64x core
Commit 02a397d1 authored by Sebastian Owarzany's avatar Sebastian Owarzany
Browse files
Options

hdl/rtl/xvme64x_core.vhd | hdl/rtl/vme64x_core_verilog.vhd add default return for functions

parent fbd7dbbf
Hide whitespace changes
Inline Side-by-side
Showing with 6 additions and 3 deletions
hdl/rtl/vme64x_core_verilog.vhd
View file @ 02a397d1
...@@ -111,7 +111,7 @@ entity vme64x_core_verilog is ...@@ -111,7 +111,7 @@ entity vme64x_core_verilog is
user_csr_we_o : out std_logic; user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2); user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : std_logic_vector(7 downto 0) := (others => '0')); user_cr_data_i : std_logic_vector(7 downto 0) := (others => '0'));
function nat_to_bool(X : natural) function nat_to_bool(X : natural)
return boolean is return boolean is
begin begin
...@@ -131,7 +131,9 @@ entity vme64x_core_verilog is ...@@ -131,7 +131,9 @@ entity vme64x_core_verilog is
if X = "BYTE" then if X = "BYTE" then
return BYTE ; return BYTE ;
end if; end if;
return BYTE ;
end string_to_wb_grn ; end string_to_wb_grn ;
function string_to_wb_mode(X : string) function string_to_wb_mode(X : string)
return t_wishbone_interface_mode is return t_wishbone_interface_mode is
begin begin
...@@ -141,6 +143,7 @@ entity vme64x_core_verilog is ...@@ -141,6 +143,7 @@ entity vme64x_core_verilog is
if X = "PIPELINED" then if X = "PIPELINED" then
return PIPELINED ; return PIPELINED ;
end if; end if;
return PIPELINED ;
end string_to_wb_mode ; end string_to_wb_mode ;
end vme64x_core_verilog; end vme64x_core_verilog;
......
hdl/rtl/xvme64x_core.vhd
View file @ 02a397d1
...@@ -120,7 +120,6 @@ entity xvme64x_core is ...@@ -120,7 +120,6 @@ entity xvme64x_core is
g_END_SN : std_logic_vector(23 downto 0) := x"000000"; g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_USE_CUSTOM_ADER : Boolean := false; g_USE_CUSTOM_ADER : Boolean := false;
-- Function decoder parameters. -- Function decoder parameters.
g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default); g_DECODER : t_vme64x_decoder_arr := c_vme64x_decoders_default);
port ( port (
...@@ -149,7 +148,7 @@ entity xvme64x_core is ...@@ -149,7 +148,7 @@ entity xvme64x_core is
irq_ack_o : out std_logic; irq_ack_o : out std_logic;
ader_i : in t_ader_array(0 to 7) := c_default_ader_array; ader_i : in t_ader_array(0 to 7) := c_default_ader_array;
-- User CSR -- User CSR
-- The following signals are used when g_USER_CSR_EXT = true -- The following signals are used when g_USER_CSR_EXT = true
-- otherwise they are connected to the internal user CSR. -- otherwise they are connected to the internal user CSR.
...@@ -192,6 +191,7 @@ architecture rtl of xvme64x_core is ...@@ -192,6 +191,7 @@ architecture rtl of xvme64x_core is
return i; return i;
end if; end if;
end loop; end loop;
return 0;
end least_set_bit; end least_set_bit;
-- Compute the ADER for each function if CR/CSR is not used. For example: -- Compute the ADER for each function if CR/CSR is not used. For example:
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment