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VME64x core
Commit 0b5cb429 authored by Tom Levens's avatar Tom Levens
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Implement DFS and FAF in CR/CSR 

Implements DFS feature and FAF in CR/CSR. Note that the DFS is still
interpreted incorrectly by the function decoders.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent a293bef9
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Showing with 596 additions and 286 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 0b5cb429
...@@ -252,16 +252,34 @@ entity VME64xCore_Top is ...@@ -252,16 +252,34 @@ entity VME64xCore_Top is
STALL_i : in std_logic; STALL_i : in std_logic;
-- For the swapper -- For the swapper
endian_i : in std_logic_vector(2 downto 0); endian_i : in std_logic_vector(2 downto 0) := (others => '0');
-- User CR/CSR -- User CR/CSR
user_csr_addr_o : out std_logic_vector(18 downto 2); user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0); user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0); user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic; user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2); user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0); user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
-- IRQ Generator -- IRQ Generator
irq_ack_o : out std_logic; -- when the IRQ controller acknowledges the irq_ack_o : out std_logic; -- when the IRQ controller acknowledges the
...@@ -273,8 +291,8 @@ entity VME64xCore_Top is ...@@ -273,8 +291,8 @@ entity VME64xCore_Top is
-- Controller which asserts one of the IRQ -- Controller which asserts one of the IRQ
-- lines. -- lines.
irq_level_i : in std_logic_vector(7 downto 0); irq_level_i : in std_logic_vector(7 downto 0) := (others => '0');
irq_vector_i : in std_logic_vector(7 downto 0) irq_vector_i : in std_logic_vector(7 downto 0) := (others => '0')
); );
end VME64xCore_Top; end VME64xCore_Top;
...@@ -301,14 +319,14 @@ architecture RTL of VME64xCore_Top is ...@@ -301,14 +319,14 @@ architecture RTL of VME64xCore_Top is
signal s_cr_csr_data_o : std_logic_vector( 7 downto 0); signal s_cr_csr_data_o : std_logic_vector( 7 downto 0);
signal s_cr_csr_data_i : std_logic_vector( 7 downto 0); signal s_cr_csr_data_i : std_logic_vector( 7 downto 0);
signal s_cr_csr_we : std_logic; signal s_cr_csr_we : std_logic;
signal s_ader0 : std_logic_vector(31 downto 0); signal s_f0_ader : std_logic_vector(31 downto 0);
signal s_ader1 : std_logic_vector(31 downto 0); signal s_f1_ader : std_logic_vector(31 downto 0);
signal s_ader2 : std_logic_vector(31 downto 0); signal s_f2_ader : std_logic_vector(31 downto 0);
signal s_ader3 : std_logic_vector(31 downto 0); signal s_f3_ader : std_logic_vector(31 downto 0);
signal s_ader4 : std_logic_vector(31 downto 0); signal s_f4_ader : std_logic_vector(31 downto 0);
signal s_ader5 : std_logic_vector(31 downto 0); signal s_f5_ader : std_logic_vector(31 downto 0);
signal s_ader6 : std_logic_vector(31 downto 0); signal s_f6_ader : std_logic_vector(31 downto 0);
signal s_ader7 : std_logic_vector(31 downto 0); signal s_f7_ader : std_logic_vector(31 downto 0);
signal s_module_reset : std_logic; signal s_module_reset : std_logic;
signal s_module_enable : std_logic; signal s_module_enable : std_logic;
signal s_bar : std_logic_vector(4 downto 0); signal s_bar : std_logic_vector(4 downto 0);
...@@ -427,14 +445,14 @@ begin ...@@ -427,14 +445,14 @@ begin
cr_csr_data_i => s_cr_csr_data_o, cr_csr_data_i => s_cr_csr_data_o,
cr_csr_data_o => s_cr_csr_data_i, cr_csr_data_o => s_cr_csr_data_i,
cr_csr_we_o => s_cr_csr_we, cr_csr_we_o => s_cr_csr_we,
ader0_i => s_ader0, f0_ader_i => s_f0_ader,
ader1_i => s_ader1, f1_ader_i => s_f1_ader,
ader2_i => s_ader2, f2_ader_i => s_f2_ader,
ader3_i => s_ader3, f3_ader_i => s_f3_ader,
ader4_i => s_ader4, f4_ader_i => s_f4_ader,
ader5_i => s_ader5, f5_ader_i => s_f5_ader,
ader6_i => s_ader6, f6_ader_i => s_f6_ader,
ader7_i => s_ader7, f7_ader_i => s_f7_ader,
endian_i => endian_i, endian_i => endian_i,
module_enable_i => s_module_enable, module_enable_i => s_module_enable,
bar_i => s_bar bar_i => s_bar
...@@ -501,28 +519,51 @@ begin ...@@ -501,28 +519,51 @@ begin
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
Inst_VME_CR_CSR_Space : VME_CR_CSR_Space Inst_VME_CR_CSR_Space : VME_CR_CSR_Space
generic map ( generic map (
g_beg_user_cr => g_beg_user_cr, g_manufacturer_id => g_manufacturer_id,
g_end_user_cr => g_end_user_cr, g_board_id => g_board_id,
g_beg_cram => g_beg_cram, g_revision_id => g_revision_id,
g_end_cram => g_end_cram, g_program_id => g_program_id,
g_beg_user_csr => g_beg_user_csr, g_ascii_ptr => g_ascii_ptr,
g_end_user_csr => g_end_user_csr, g_beg_user_cr => g_beg_user_cr,
g_cr_space => f_vme_cr_encode( g_end_user_cr => g_end_user_cr,
g_manufacturer_id, g_board_id, g_revision_id, g_program_id, g_beg_cram => g_beg_cram,
g_ascii_ptr, g_end_cram => g_end_cram,
g_beg_user_cr, g_end_user_cr, g_beg_user_csr => g_beg_user_csr,
g_beg_cram, g_end_cram, g_end_user_csr => g_end_user_csr,
g_beg_user_csr, g_end_user_csr, g_beg_sn => g_beg_sn,
g_beg_sn, g_end_sn, g_end_sn => g_end_sn,
g_f0_adem, g_f0_amcap, g_f0_xamcap, g_f0_dawpr, g_f0_adem => g_f0_adem,
g_f1_adem, g_f1_amcap, g_f1_xamcap, g_f1_dawpr, g_f0_amcap => g_f0_amcap,
g_f2_adem, g_f2_amcap, g_f2_xamcap, g_f2_dawpr, g_f0_xamcap => g_f0_xamcap,
g_f3_adem, g_f3_amcap, g_f3_xamcap, g_f3_dawpr, g_f0_dawpr => g_f0_dawpr,
g_f4_adem, g_f4_amcap, g_f4_xamcap, g_f4_dawpr, g_f1_adem => g_f1_adem,
g_f5_adem, g_f5_amcap, g_f5_xamcap, g_f5_dawpr, g_f1_amcap => g_f1_amcap,
g_f6_adem, g_f6_amcap, g_f6_xamcap, g_f6_dawpr, g_f1_xamcap => g_f1_xamcap,
g_f7_adem, g_f7_amcap, g_f7_xamcap, g_f7_dawpr g_f1_dawpr => g_f1_dawpr,
) g_f2_adem => g_f2_adem,
g_f2_amcap => g_f2_amcap,
g_f2_xamcap => g_f2_xamcap,
g_f2_dawpr => g_f2_dawpr,
g_f3_adem => g_f3_adem,
g_f3_amcap => g_f3_amcap,
g_f3_xamcap => g_f3_xamcap,
g_f3_dawpr => g_f3_dawpr,
g_f4_adem => g_f4_adem,
g_f4_amcap => g_f4_amcap,
g_f4_xamcap => g_f4_xamcap,
g_f4_dawpr => g_f4_dawpr,
g_f5_adem => g_f5_adem,
g_f5_amcap => g_f5_amcap,
g_f5_xamcap => g_f5_xamcap,
g_f5_dawpr => g_f5_dawpr,
g_f6_adem => g_f6_adem,
g_f6_amcap => g_f6_amcap,
g_f6_xamcap => g_f6_xamcap,
g_f6_dawpr => g_f6_dawpr,
g_f7_adem => g_f7_adem,
g_f7_amcap => g_f7_amcap,
g_f7_xamcap => g_f7_xamcap,
g_f7_dawpr => g_f7_dawpr
) )
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
...@@ -549,14 +590,32 @@ begin ...@@ -549,14 +590,32 @@ begin
user_cr_addr_o => user_cr_addr_o, user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i, user_cr_data_i => user_cr_data_i,
ader0_o => s_ader0, f0_ader_o => s_f0_ader,
ader1_o => s_ader1, f1_ader_o => s_f1_ader,
ader2_o => s_ader2, f2_ader_o => s_f2_ader,
ader3_o => s_ader3, f3_ader_o => s_f3_ader,
ader4_o => s_ader4, f4_ader_o => s_f4_ader,
ader5_o => s_ader5, f5_ader_o => s_f5_ader,
ader6_o => s_ader6, f6_ader_o => s_f6_ader,
ader7_o => s_ader7 f7_ader_o => s_f7_ader,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
); );
end RTL; end RTL;
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ 0b5cb429
...@@ -136,7 +136,7 @@ begin ...@@ -136,7 +136,7 @@ begin
elsif decode = '1' then elsif decode = '1' then
for i in AmMatch'range loop for i in AmMatch'range loop
if DFS_i(i) = '1' then if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then if s_FUNC_ADER(i)(ADER_XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i); AmMatch(i) <= s_amcap_match(i);
else else
...@@ -150,7 +150,7 @@ begin ...@@ -150,7 +150,7 @@ begin
end if; end if;
end if; end if;
else else
if s_FUNC_ADER(i)(XAM_MODE) = '1' then if s_FUNC_ADER(i)(ADER_XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i); AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else else
AmMatch(i) <= s_amcap_match(i); AmMatch(i) <= s_amcap_match(i);
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 0b5cb429
This diff is collapsed.
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 0b5cb429
...@@ -318,7 +318,7 @@ begin ...@@ -318,7 +318,7 @@ begin
s_FUNC_ADEM(7) <= unsigned(Adem7); s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(DFS); DFS_o(i) <= s_FUNC_ADEM(i)(ADEM_DFS);
end generate GDFS; end generate GDFS;
GADER_64 : for i in 0 to 6 generate GADER_64 : for i in 0 to 6 generate
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 0b5cb429
...@@ -149,14 +149,14 @@ entity VME_bus is ...@@ -149,14 +149,14 @@ entity VME_bus is
cr_csr_data_i : in std_logic_vector( 7 downto 0); cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0); cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_o : out std_logic; cr_csr_we_o : out std_logic;
ader0_i : in std_logic_vector(31 downto 0); f0_ader_i : in std_logic_vector(31 downto 0);
ader1_i : in std_logic_vector(31 downto 0); f1_ader_i : in std_logic_vector(31 downto 0);
ader2_i : in std_logic_vector(31 downto 0); f2_ader_i : in std_logic_vector(31 downto 0);
ader3_i : in std_logic_vector(31 downto 0); f3_ader_i : in std_logic_vector(31 downto 0);
ader4_i : in std_logic_vector(31 downto 0); f4_ader_i : in std_logic_vector(31 downto 0);
ader5_i : in std_logic_vector(31 downto 0); f5_ader_i : in std_logic_vector(31 downto 0);
ader6_i : in std_logic_vector(31 downto 0); f6_ader_i : in std_logic_vector(31 downto 0);
ader7_i : in std_logic_vector(31 downto 0); f7_ader_i : in std_logic_vector(31 downto 0);
endian_i : in std_logic_vector(2 downto 0); endian_i : in std_logic_vector(2 downto 0);
module_enable_i : in std_logic; module_enable_i : in std_logic;
bar_i : in std_logic_vector(4 downto 0) bar_i : in std_logic_vector(4 downto 0)
...@@ -1120,14 +1120,14 @@ begin ...@@ -1120,14 +1120,14 @@ begin
decode => s_decode, decode => s_decode,
ModuleEnable => module_enable_i, ModuleEnable => module_enable_i,
Addr => std_logic_vector(s_locAddr), Addr => std_logic_vector(s_locAddr),
Ader0 => ader0_i, Ader0 => f0_ader_i,
Ader1 => ader1_i, Ader1 => f1_ader_i,
Ader2 => ader2_i, Ader2 => f2_ader_i,
Ader3 => ader3_i, Ader3 => f3_ader_i,
Ader4 => ader4_i, Ader4 => f4_ader_i,
Ader5 => ader5_i, Ader5 => f5_ader_i,
Ader6 => ader6_i, Ader6 => f6_ader_i,
Ader7 => ader7_i, Ader7 => f7_ader_i,
Adem0 => g_f0_adem, Adem0 => g_f0_adem,
Adem1 => g_f1_adem, Adem1 => g_f1_adem,
Adem2 => g_f2_adem, Adem2 => g_f2_adem,
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 0b5cb429
This diff is collapsed.
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ 0b5cb429
...@@ -40,6 +40,7 @@ entity xvme64x_core is ...@@ -40,6 +40,7 @@ entity xvme64x_core is
g_clock_period : integer := c_clk_period; g_clock_period : integer := c_clk_period;
g_wb_data_width : integer := c_wishbone_data_width; g_wb_data_width : integer := c_wishbone_data_width;
g_wb_addr_width : integer := c_wishbone_address_width; g_wb_addr_width : integer := c_wishbone_address_width;
g_user_csr_ext : boolean := false;
-- CR/CSR -- CR/CSR
g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id; g_manufacturer_id : std_logic_vector(23 downto 0) := c_cern_id;
...@@ -136,7 +137,33 @@ entity xvme64x_core is ...@@ -136,7 +137,33 @@ entity xvme64x_core is
master_i : in t_wishbone_master_in; master_i : in t_wishbone_master_in;
irq_i : in std_logic; irq_i : in std_logic;
irq_ack_o : out std_logic irq_ack_o : out std_logic;
user_csr_addr_o : out std_logic_vector(18 downto 2);
user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0')
); );
end xvme64x_core; end xvme64x_core;
...@@ -144,15 +171,15 @@ end xvme64x_core; ...@@ -144,15 +171,15 @@ end xvme64x_core;
architecture wrapper of xvme64x_core is architecture wrapper of xvme64x_core is
signal dat_out, signal dat_out,
dat_in : std_logic_vector(31 downto 0); dat_in : std_logic_vector(31 downto 0);
signal adr_out : std_logic_vector(31 downto 0); signal adr_out : std_logic_vector(31 downto 0);
signal irq_vector, signal irq_vector,
irq_level : std_logic_vector( 7 downto 0); irq_level : std_logic_vector( 7 downto 0);
signal endian : std_logic_vector( 2 downto 0); signal endian : std_logic_vector( 2 downto 0);
signal user_csr_addr : std_logic_vector(18 downto 2); signal user_csr_addr : std_logic_vector(18 downto 2);
signal user_csr_data_i, signal user_csr_data_in,
user_csr_data_o : std_logic_vector( 7 downto 0); user_csr_data_out : std_logic_vector( 7 downto 0);
signal user_csr_we : std_logic; signal user_csr_we : std_logic;
begin -- wrapper begin -- wrapper
...@@ -253,16 +280,34 @@ begin -- wrapper ...@@ -253,16 +280,34 @@ begin -- wrapper
endian_i => endian, endian_i => endian,
user_csr_addr_o => user_csr_addr, user_csr_addr_o => user_csr_addr,
user_csr_data_i => user_csr_data_o, user_csr_data_i => user_csr_data_in,
user_csr_data_o => user_csr_data_i, user_csr_data_o => user_csr_data_out,
user_csr_we_o => user_csr_we, user_csr_we_o => user_csr_we,
user_cr_addr_o => open, user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => x"00", user_cr_data_i => user_cr_data_i,
irq_i => irq_i, irq_i => irq_i,
irq_ack_o => irq_ack_o, irq_ack_o => irq_ack_o,
irq_vector_i => irq_vector, irq_vector_i => irq_vector,
irq_level_i => irq_level irq_level_i => irq_level,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i
); );
master_o.dat <= dat_out(31 downto 0); master_o.dat <= dat_out(31 downto 0);
...@@ -270,22 +315,31 @@ begin -- wrapper ...@@ -270,22 +315,31 @@ begin -- wrapper
master_o.adr <= adr_out(29 downto 0) & "00"; master_o.adr <= adr_out(29 downto 0) & "00";
dat_in <= master_i.dat; dat_in <= master_i.dat;
U_User_CSR : VME_User_CSR gen_user_cr_csr: if g_user_csr_ext = false generate
generic map ( U_User_CSR : VME_User_CSR
g_wb_data_width => g_wb_data_width generic map (
) g_wb_data_width => g_wb_data_width
port map ( )
clk_i => clk_i, port map (
rst_n_i => rst_n_i, clk_i => clk_i,
addr_i => user_csr_addr, rst_n_i => rst_n_i,
data_i => user_csr_data_i, addr_i => user_csr_addr,
data_o => user_csr_data_o, data_i => user_csr_data_out,
we_i => user_csr_we, data_o => user_csr_data_in,
irq_vector_o => irq_vector, we_i => user_csr_we,
irq_level_o => irq_level, irq_vector_o => irq_vector,
endian_o => endian, irq_level_o => irq_level,
time_i => x"0000000000", endian_o => endian,
bytes_i => x"0000" time_i => x"0000000000",
); bytes_i => x"0000"
);
end generate;
gen_no_user_cr_csr: if g_user_csr_ext = true generate
user_csr_data_in <= user_csr_data_i;
end generate;
user_csr_addr_o <= user_csr_addr;
user_csr_data_o <= user_csr_data_out;
user_csr_we_o <= user_csr_we;
end wrapper; end wrapper;
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @ 0b5cb429
...@@ -81,6 +81,7 @@ package xvme64x_core_pkg is ...@@ -81,6 +81,7 @@ package xvme64x_core_pkg is
g_clock : integer; g_clock : integer;
g_wb_data_width : integer; g_wb_data_width : integer;
g_wb_addr_width : integer; g_wb_addr_width : integer;
g_user_csr_ext : boolean;
g_manufacturer_id : std_logic_vector(23 downto 0); g_manufacturer_id : std_logic_vector(23 downto 0);
g_board_id : std_logic_vector(31 downto 0); g_board_id : std_logic_vector(31 downto 0);
g_revision_id : std_logic_vector(31 downto 0); g_revision_id : std_logic_vector(31 downto 0);
...@@ -131,7 +132,6 @@ package xvme64x_core_pkg is ...@@ -131,7 +132,6 @@ package xvme64x_core_pkg is
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
rst_n_o : out std_logic; rst_n_o : out std_logic;
VME_AS_n_i : in std_logic; VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic; VME_WRITE_n_i : in std_logic;
...@@ -157,12 +157,32 @@ package xvme64x_core_pkg is ...@@ -157,12 +157,32 @@ package xvme64x_core_pkg is
VME_DATA_OE_N_o : out std_logic; VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic; VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic; VME_ADDR_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_o : out t_wishbone_master_out; master_i : in t_wishbone_master_in;
master_i : in t_wishbone_master_in; irq_i : in std_logic;
irq_ack_o : out std_logic;
irq_i : in std_logic; user_csr_addr_o : out std_logic_vector(18 downto 2);
irq_ack_o : out std_logic user_csr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
user_csr_data_o : out std_logic_vector( 7 downto 0);
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0')
); );
end component xvme64x_core; end component xvme64x_core;
......
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