hdl: further cleanup of WB INT and default value for int input when not used

73232ebd · Dimitris Lampridis · a120e226 · 73232ebd · 73232ebd · 73232ebd
Commit 73232ebd authored Mar 20, 2018 by Dimitris Lampridis
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Showing with 2 additions and 4 deletions

vme64x_core.vhd hdl/rtl/vme64x_core.vhd +0 -2

vme64x_pkg.vhd hdl/rtl/vme64x_pkg.vhd +1 -1

xvme64x_core.vhd hdl/rtl/xvme64x_core.vhd +1 -1

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--- a/hdl/rtl/vme64x_core.vhd
+++ b/hdl/rtl/vme64x_core.vhd
@@ -85,7 +85,6 @@ entity vme64x_core is
    wb_err_i        : std_logic;
    wb_rty_i        : std_logic;
    wb_stall_i      : std_logic;
-    wb_int_i        : std_logic;
    wb_dat_i        : t_wishbone_data;
    wb_cyc_o        : out std_logic;
    wb_stb_o        : out std_logic;
@@ -183,7 +182,6 @@ begin
      wb_i.err        => wb_err_i,
      wb_i.rty        => wb_rty_i,
      wb_i.stall      => wb_stall_i,
-      wb_i.int        => wb_int_i,
      wb_i.dat        => wb_dat_i,
      wb_o.cyc        => wb_cyc_o,
      wb_o.stb        => wb_stb_o,

--- a/hdl/rtl/vme64x_pkg.vhd
+++ b/hdl/rtl/vme64x_pkg.vhd
@@ -215,7 +215,7 @@ package vme64x_pkg is
      wb_i            : in  t_wishbone_master_in;
      wb_o            : out t_wishbone_master_out;
-      int_i           : in std_logic;
+      int_i           : in std_logic := '0';
      irq_ack_o       : out std_logic;

--- a/hdl/rtl/xvme64x_core.vhd
+++ b/hdl/rtl/xvme64x_core.vhd
@@ -114,7 +114,7 @@ entity xvme64x_core is
    -- Interrupt input from the master side.
    -- Previously it was part of the wishbone interface, but is now separate
    -- as interrupt is not defined by wishbone.
-    int_i           : in std_logic;
+    int_i           : in std_logic := '0';
    -- When the IRQ controller acknowledges the Interrupt cycle it sends a
    -- pulse to the IRQ Generator.