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VME64x core
Commits
8b9e164d
Commit
8b9e164d
authored
Apr 15, 2020
by
Tristan Gingold
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vme_cr_csr_space.vhd: minor refactoring.
parent
26ae1414
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vme_cr_csr_space.vhd
hdl/rtl/vme_cr_csr_space.vhd
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hdl/rtl/vme_cr_csr_space.vhd
View file @
8b9e164d
...
@@ -190,11 +190,9 @@ architecture rtl of vme_cr_csr_space is
...
@@ -190,11 +190,9 @@ architecture rtl of vme_cr_csr_space is
-- CRAM
-- CRAM
type
t_cram
is
array
(
c_CRAM_SIZE
-1
downto
0
)
of
std_logic_vector
(
7
downto
0
);
type
t_cram
is
array
(
c_CRAM_SIZE
-1
downto
0
)
of
std_logic_vector
(
7
downto
0
);
signal
s_cram
:
t_cram
;
signal
s_cram_data
:
std_logic_vector
(
7
downto
0
);
signal
s_cram_data
:
std_logic_vector
(
7
downto
0
);
signal
s_cram_waddr
:
unsigned
(
18
downto
2
);
signal
s_cram_waddr
:
unsigned
(
18
downto
2
);
signal
s_cram_raddr
:
unsigned
(
18
downto
2
);
signal
s_cram_raddr
:
unsigned
(
18
downto
2
);
signal
s_cram_we
:
std_logic
;
-- Addresses
-- Addresses
subtype
crcsr_addr
is
unsigned
(
18
downto
2
);
subtype
crcsr_addr
is
unsigned
(
18
downto
2
);
...
@@ -507,6 +505,9 @@ begin
...
@@ -507,6 +505,9 @@ begin
-- CRAM
-- CRAM
------------------------------------------------------------------------------
------------------------------------------------------------------------------
gen_cram_ena
:
if
c_CRAM_ENA
=
true
generate
gen_cram_ena
:
if
c_CRAM_ENA
=
true
generate
signal
s_cram
:
t_cram
;
signal
s_cram_we
:
std_logic
;
begin
s_cram_access
<=
'1'
when
s_addr
>=
c_BEG_CRAM
and
s_cram_access
<=
'1'
when
s_addr
>=
c_BEG_CRAM
and
s_addr
<=
c_END_CRAM
s_addr
<=
c_END_CRAM
else
'0'
;
else
'0'
;
...
...
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