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VME64x core
Commit ae18039d authored by Tom Levens's avatar Tom Levens
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Removed unused debug signals from VME_bus.vhd 

Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent dafbb793
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Showing with 7 additions and 32 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ ae18039d
...@@ -183,11 +183,9 @@ entity VME64xCore_Top is ...@@ -183,11 +183,9 @@ entity VME64xCore_Top is
-- IRQ Generator -- IRQ Generator
INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt
-- cycle it sends a pulse to the IRQ Generator -- cycle it sends a pulse to the IRQ Generator
IRQ_i : in std_logic; -- Interrupt request; the IRQ Generator/your Wb application IRQ_i : in std_logic -- Interrupt request; the IRQ Generator/your Wb application
-- sends a pulse to the IRQ Controller which asserts one of -- sends a pulse to the IRQ Controller which asserts one of
-- the IRQ lines. -- the IRQ lines.
-- Added by Davide for debug:
debug : out std_logic_vector(7 downto 0)
); );
end VME64xCore_Top; end VME64xCore_Top;
...@@ -255,8 +253,6 @@ architecture RTL of VME64xCore_Top is ...@@ -255,8 +253,6 @@ architecture RTL of VME64xCore_Top is
signal s_ModuleEnable : std_logic; signal s_ModuleEnable : std_logic;
signal s_Endian : std_logic_vector(2 downto 0); signal s_Endian : std_logic_vector(2 downto 0);
signal s_BAR : std_logic_vector(4 downto 0); signal s_BAR : std_logic_vector(4 downto 0);
signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
-- Oversampled input signals -- Oversampled input signals
signal VME_RST_n_oversampled : std_logic; signal VME_RST_n_oversampled : std_logic;
...@@ -410,11 +406,7 @@ begin ...@@ -410,11 +406,7 @@ begin
ModuleEnable => s_ModuleEnable, ModuleEnable => s_ModuleEnable,
Endian_i => s_Endian, Endian_i => s_Endian,
Sw_Reset => s_Sw_Reset, Sw_Reset => s_Sw_Reset,
BAR_i => s_BAR, BAR_i => s_BAR
numBytes => s_bytes,
transfTime => s_time,
-- debug
leds => debug
); );
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
...@@ -498,8 +490,8 @@ begin ...@@ -498,8 +490,8 @@ begin
Endian_o => s_Endian, Endian_o => s_Endian,
BAR_o => s_BAR, BAR_o => s_BAR,
INT_Level => s_INT_Level, INT_Level => s_INT_Level,
numBytes => s_bytes, numBytes => (others => '0'),
transfTime => s_time, transfTime => (others => '0'),
INT_Vector => s_INT_Vector INT_Vector => s_INT_Vector
); );
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ ae18039d
...@@ -34,15 +34,6 @@ ...@@ -34,15 +34,6 @@
-- one Slave can answer to the Master! | -- one Slave can answer to the Master! |
-- In the right side you can see the WB Master who implements the Wb Pipelined | -- In the right side you can see the WB Master who implements the Wb Pipelined |
-- single read/write protocol. -- single read/write protocol.
--
-- led 0 <-- error flag
-- led 1 <-- last access: CR/CSR
-- led 2 <-- last access: WB SINGLE access
-- led 3 <-- last access: WB BLT access
-- led 4 <-- last access: WB MBLT access
-- led 5 <-- WB data bus 32 bits
-- led 6 <-- Module enable
-- led 7 <-- flashing
-- Each VME board plugged in a slot acts as a VME slave module and it has only -- Each VME board plugged in a slot acts as a VME slave module and it has only
-- one CR/CSR space (conforming with the specification) so only one FPGA at time -- one CR/CSR space (conforming with the specification) so only one FPGA at time
-- must drive the output lines on the VME bus; only one FPGA at time can carry -- must drive the output lines on the VME bus; only one FPGA at time can carry
...@@ -153,11 +144,7 @@ entity VME_bus is ...@@ -153,11 +144,7 @@ entity VME_bus is
ModuleEnable : in std_logic; ModuleEnable : in std_logic;
Endian_i : in std_logic_vector(2 downto 0); Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic; Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0); BAR_i : in std_logic_vector(4 downto 0)
numBytes : out std_logic_vector(12 downto 0) := (others => '0'); -- TODO: what's this?
transfTime : out std_logic_vector(39 downto 0) := (others => '0'); -- TODO: what's this?
-- Debug
leds : out std_logic_vector(7 downto 0) := (others => '0') -- not used
); );
end VME_bus; end VME_bus;
--=========================================================================== --===========================================================================
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ ae18039d
...@@ -482,10 +482,7 @@ package vme64x_pack is ...@@ -482,10 +482,7 @@ package vme64x_pack is
en_wr_CSR : out std_logic; en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0); CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0); CSRData_o : out std_logic_vector(7 downto 0);
err_flag_o : out std_logic; err_flag_o : out std_logic
numBytes : out std_logic_vector(12 downto 0);
transfTime : out std_logic_vector(39 downto 0);
leds : out std_logic_vector(7 downto 0)
); );
end component VME_bus; end component VME_bus;
......
hdl/vme64x-core/rtl/xvme64x_core.vhd
View file @ ae18039d
...@@ -138,8 +138,7 @@ architecture wrapper of xvme64x_core is ...@@ -138,8 +138,7 @@ architecture wrapper of xvme64x_core is
WE_o : out std_logic; WE_o : out std_logic;
STALL_i : in std_logic; STALL_i : in std_logic;
INT_ack_o : out std_logic; INT_ack_o : out std_logic;
IRQ_i : in std_logic; IRQ_i : in std_logic);
debug : out std_logic_vector(7 downto 0));
end component; end component;
signal dat_out, dat_in : std_logic_vector(31 downto 0); signal dat_out, dat_in : std_logic_vector(31 downto 0);
......
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