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White Rabbit core collection
Commit f1b7521d authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'greg-cute-1p' into proposed_master

parents 9347bd38 edd3bd31
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board/cute/Manifest.py 0 → 100644
View file @ f1b7521d
files = [
"wr_cute_pkg.vhd",
"xwrc_board_cute.vhd",
]
modules = {
"local" : [
"../common",
]
}
board/cute/wr_cute_pkg.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CUTE package
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : wr_cute_pkg.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Company : Tsinghua Univ. (DEP)
-- Created : 2018-07-14
-- Last update: 2018-07-14
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.streamers_pkg.all;
package wr_cute_pkg is
component xwrc_board_cute is
generic(
g_simulation : integer := 0;
g_with_external_clock_input : boolean := false;
g_aux_clks : integer := 0;
g_fabric_iface : t_board_fabric_iface := plain;
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
g_dpram_initf : string := "default_xilinx";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- CUTE special
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_10m_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_10m_ext_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '0';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '0';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
eeprom_sda_i : in std_logic := '1';
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic := '1';
eeprom_scl_o : out std_logic;
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic := '1';
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
link_ok_o : out std_logic);
end component xwrc_board_cute;
constant c_xwb_tcpip_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000ff",
product => (
vendor_id => x"0000000000001103", -- thu
device_id => x"c0413599",
version => x"00000001",
date => x"20160424",
name => "wr-tcp-ip-stack ")));
end wr_cute_pkg;
board/cute/xwrc_board_cute.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : WRPC Wrapper for CUTE
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : xwrc_board_cute.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>, Greg Daniluk <grzegorz.daniluk@cern.ch>
-- Company : Tsinghua Univ. (DEP), CERN
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
-- needed to operate the core on the CUTE board.
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.streamers_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_cute_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xwrc_board_cute is
generic(
-- set to 1 to speed up some initialization processes during simulation
g_simulation : integer := 0;
-- Select whether to include external ref clock input
g_with_external_clock_input : boolean := false;
-- Number of aux clocks syntonized by WRPC to WR timebase
g_aux_clks : integer := 0;
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_fabric_iface : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
-- memory initialisation file for embedded CPU
g_dpram_initf : string := "default_xilinx";
-- identification (id and ver) of the layout of words in the generic diag interface
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
---------------------------------------------------------------------------
-- cute special
---------------------------------------------------------------------------
g_cute_version : string := "2.2";
g_sfp0_enable : integer := 1;
g_sfp1_enable : integer := 0;
g_phy_refclk_sel : integer := 0;
g_multiboot_enable : boolean := false
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset input (active low, can be async)
areset_n_i : in std_logic;
-- Optional reset input active low with rising edge detection. Does not
-- reset PLLs.
areset_edge_n_i : in std_logic := '1';
-- Clock inputs from the board
clk_20m_vcxo_i : in std_logic;
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtp0_p_i : in std_logic :='0';
clk_125m_gtp0_n_i : in std_logic :='0';
clk_125m_gtp1_p_i : in std_logic :='0';
clk_125m_gtp1_n_i : in std_logic :='0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input (g_with_external_clock_input = TRUE)
clk_10m_ext_i : in std_logic := '0';
-- External PPS input (g_with_external_clock_input = TRUE)
pps_ext_i : in std_logic := '0';
-- 62.5MHz sys clock output
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- 10MHz ext clock output
clk_10m_ext_o : out std_logic;
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
plldac_clr_n_o : out std_logic;
plldac_load_n_o : out std_logic;
plldac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver and SFP management info
---------------------------------------------------------------------------
sfp0_txp_o : out std_logic;
sfp0_txn_o : out std_logic;
sfp0_rxp_i : in std_logic := '0';
sfp0_rxn_i : in std_logic := '0';
sfp0_det_i : in std_logic := '1';
sfp0_sda_i : in std_logic := '1';
sfp0_sda_o : out std_logic;
sfp0_scl_i : in std_logic := '1';
sfp0_scl_o : out std_logic;
sfp0_rate_select_o : out std_logic;
sfp0_tx_fault_i : in std_logic := '0';
sfp0_tx_disable_o : out std_logic;
sfp0_los_i : in std_logic := '0';
sfp1_txp_o : out std_logic;
sfp1_txn_o : out std_logic;
sfp1_rxp_i : in std_logic := '0';
sfp1_rxn_i : in std_logic := '0';
sfp1_det_i : in std_logic := '1';
sfp1_sda_i : in std_logic := '1';
sfp1_sda_o : out std_logic;
sfp1_scl_i : in std_logic := '1';
sfp1_scl_o : out std_logic;
sfp1_rate_select_o : out std_logic;
sfp1_tx_fault_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
sfp1_los_i : in std_logic := '0';
---------------------------------------------------------------------------
-- I2C EEPROM
---------------------------------------------------------------------------
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_i : in std_logic;
onewire_oen_o : out std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
---------------------------------------------------------------------------
-- External WB interface
---------------------------------------------------------------------------
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_dummy_snk_in;
---------------------------------------------------------------------------
-- WR streamers (when g_fabric_iface = "streamers")
---------------------------------------------------------------------------
wrs_tx_data_i : in std_logic_vector(g_tx_streamer_params.data_width-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_tx_streamer_cfg_default;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
---------------------------------------------------------------------------
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
---------------------------------------------------------------------------
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- Generic diagnostics interface (access from WRPC via SNMP or uart console
---------------------------------------------------------------------------
aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
---------------------------------------------------------------------------
-- Aux clocks control
---------------------------------------------------------------------------
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
---------------------------------------------------------------------------
-- External Tx Timestamping I/F
---------------------------------------------------------------------------
timestamps_o : out t_txtsu_timestamp;
timestamps_ack_i : in std_logic := '1';
-----------------------------------------
-- Timestamp helper signals, used for Absolute Calibration
-----------------------------------------
abscal_txts_o : out std_logic;
abscal_rxts_o : out std_logic;
---------------------------------------------------------------------------
-- Pause Frame Control
---------------------------------------------------------------------------
fc_tx_pause_req_i : in std_logic := '0';
fc_tx_pause_delay_i : in std_logic_vector(15 downto 0) := x"0000";
fc_tx_pause_ready_o : out std_logic;
---------------------------------------------------------------------------
-- Timecode I/F
---------------------------------------------------------------------------
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
---------------------------------------------------------------------------
-- Buttons, LEDs and PPS output
---------------------------------------------------------------------------
led_act_o : out std_logic;
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o: out std_logic;
-- Link ok indication
link_ok_o : out std_logic
);
end entity xwrc_board_cute;
architecture struct of xwrc_board_cute is
------------------------------------------------------------------------------
-- components declaration
------------------------------------------------------------------------------
component cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end component cute_serial_dac_arb;
component oserdes_4_to_1 is
generic(
sys_w : integer := 1;
dev_w : integer := 4);
port(
data_out_from_device : in std_logic_vector(dev_w-1 downto 0);
data_out_to_pins : out std_logic_vector(sys_w-1 downto 0);
delay_reset : in std_logic;
clk_in : in std_logic;
pll_locked : in std_logic;
clk_div_in : in std_logic;
io_reset : in std_logic);
end component;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
constant c_AUX_500M_CFG : t_auxpll_cfg := (
enabled => TRUE,
bufg_en => FALSE,
divide => 2);
constant c_AUX_CFG_ARRAY : t_auxpll_cfg_array := (0=>c_AUX_500M_CFG, others=>c_AUXPLL_CFG_DEFAULT);
-- IBUFDS
signal clk_125m_pllref_buf : std_logic;
-- PLLs, clocks
signal clk_125m_gtp_p : std_logic;
signal clk_125m_gtp_n : std_logic;
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_20m : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
signal clk_pll_aux_out : std_logic_vector(3 downto 0);
-- Reset logic
signal areset_edge_ppulse : std_logic;
signal rst_62m5_n : std_logic;
signal rstlogic_arst_n : std_logic;
signal rstlogic_clk_in : std_logic_vector(1 downto 0);
signal rstlogic_rst_out : std_logic_vector(1 downto 0);
-- PLL DAC ARB
signal dac_hpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_load_p1 : std_logic;
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal dac_val1_data : std_logic_vector(15 downto 0);
signal dac_val2_data : std_logic_vector(15 downto 0);
signal dac_val1_load : std_logic;
signal dac_val2_load : std_logic;
-- OneWire
signal onewire_in : std_logic_vector(1 downto 0);
signal onewire_en : std_logic_vector(1 downto 0);
-- PHY
signal phy8_to_wrc : t_phy_8bits_to_wrc;
signal phy8_from_wrc : t_phy_8bits_from_wrc;
-- External reference
signal ext_ref_mul : std_logic;
signal ext_ref_mul_locked : std_logic;
signal ext_ref_mul_stopped : std_logic;
signal ext_ref_rst : std_logic;
-- CUTE-WR specific stuff
signal sfp_txp_out : std_logic;
signal sfp_txn_out : std_logic;
signal sfp_rxp_in : std_logic;
signal sfp_rxn_in : std_logic;
signal sfp_det_in : std_logic;
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
signal sfp_tx_fault_in : std_logic;
signal sfp_tx_disable_out : std_logic;
signal sfp_los_in : std_logic;
signal tm_time_valid : std_logic;
-- ext 10M clock output
constant c_DATA_W : integer := 4; -- parallel data width going to serdes
constant c_HALF : integer := 25; -- default high/low width for 10MHz
signal rst_oserdes : std_logic;
signal pll_aux_locked : std_logic;
signal sd_out : std_logic_vector(0 downto 0);
signal sd_data : std_logic_vector(c_DATA_W-1 downto 0);
signal aux_half_high: unsigned(15 downto 0);
signal aux_half_low : unsigned(15 downto 0);
signal aux_shift : unsigned(15 downto 0);
signal clk_realign : std_logic;
signal tm_time_valid_d1 : std_logic;
signal pps_csync : std_logic;
signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in := cc_dummy_master_in;
signal multiboot_slave_out : t_wishbone_slave_out;
signal multiboot_slave_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal multiboot_wb_out : t_wishbone_master_out;
signal multiboot_wb_in : t_wishbone_master_in;
begin -- architecture struct
-----------------------------------------------------------------------------
-- Platform-dependent part (PHY, PLLs, buffers, etc)
-----------------------------------------------------------------------------
cmp_ibufgds_pllref : IBUFGDS
generic map (
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE,
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref_buf,
I => clk_125m_pllref_p_i,
IB => clk_125m_pllref_n_i);
cmp_xwrc_platform : xwrc_platform_xilinx
generic map (
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_cfg => c_AUX_CFG_ARRAY,
g_gtp_enable_ch0 => 0,
g_gtp_enable_ch1 => 1,
g_phy_refclk_sel => g_phy_refclk_sel,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_i => clk_125m_pllref_buf,
clk_125m_gtp_p_i => clk_125m_gtp_p,
clk_125m_gtp_n_i => clk_125m_gtp_n,
sfp_txn_o => sfp_txn_out,
sfp_txp_o => sfp_txp_out,
sfp_rxn_i => sfp_rxn_in,
sfp_rxp_i => sfp_rxp_in,
sfp_tx_fault_i => sfp_tx_fault_in,
sfp_los_i => sfp_los_in,
sfp_tx_disable_o => sfp_tx_disable_out,
clk_pll_aux_o => clk_pll_aux_out,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_20m_o => clk_pll_20m,
clk_62m5_dmtd_o => clk_pll_dmtd,
pll_locked_o => pll_locked,
pll_aux_locked_o => pll_aux_locked,
clk_10m_ext_o => clk_10m_ext,
phy8_o => phy8_to_wrc,
phy8_i => phy8_from_wrc,
ext_ref_mul_o => ext_ref_mul,
ext_ref_mul_locked_o => ext_ref_mul_locked,
ext_ref_mul_stopped_o => ext_ref_mul_stopped,
ext_ref_rst_i => ext_ref_rst);
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
-----------------------------------------------------------------------------
-- SFP0/1 selection
-----------------------------------------------------------------------------
GEN_GTP0: if g_sfp0_enable = 1 generate
clk_125m_gtp_p <= clk_125m_gtp0_p_i;
clk_125m_gtp_n <= clk_125m_gtp0_n_i;
sfp0_txp_o <= sfp_txp_out;
sfp0_txn_o <= sfp_txn_out;
sfp0_sda_o <= sfp_sda_out;
sfp0_scl_o <= sfp_scl_out;
sfp0_tx_disable_o <= sfp_tx_disable_out;
sfp_rxp_in <= sfp0_rxp_i;
sfp_rxn_in <= sfp0_rxn_i;
sfp_det_in <= sfp0_det_i;
sfp_sda_in <= sfp0_sda_i;
sfp_scl_in <= sfp0_scl_i;
sfp_tx_fault_in <= sfp0_tx_fault_i;
sfp_los_in <= sfp0_los_i;
end generate;
GEN_GTP1: if g_sfp1_enable = 1 generate
clk_125m_gtp_p <= clk_125m_gtp1_p_i;
clk_125m_gtp_n <= clk_125m_gtp1_n_i;
sfp1_txp_o <= sfp_txp_out;
sfp1_txn_o <= sfp_txn_out;
sfp1_sda_o <= sfp_sda_out;
sfp1_scl_o <= sfp_scl_out;
sfp1_tx_disable_o <= sfp_tx_disable_out;
sfp_rxp_in <= sfp1_rxp_i;
sfp_rxn_in <= sfp1_rxn_i;
sfp_det_in <= sfp1_det_i;
sfp_sda_in <= sfp1_sda_i;
sfp_scl_in <= sfp1_scl_i;
sfp_tx_fault_in <= sfp1_tx_fault_i;
sfp_los_in <= sfp1_los_i;
end generate;
sfp0_rate_select_o <= '1';
sfp1_rate_select_o <= '1';
-----------------------------------------------------------------------------
-- Reset logic
-----------------------------------------------------------------------------
-- Detect when areset_edge_n_i goes high (end of reset) and use this edge to
-- generate rstlogic_arst_n. This is needed to connect optional reset like PCIe
-- reset. When baord runs standalone, we need to ignore PCIe reset being
-- constantly low.
cmp_arst_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_pll_62m5,
rst_n_i => '1',
data_i => areset_edge_n_i,
ppulse_o => areset_edge_ppulse);
-- logic AND of all async reset sources (active low)
rstlogic_arst_n <= pll_locked and areset_n_i and (not areset_edge_ppulse);
-- concatenation of all clocks required to have synced resets
rstlogic_clk_in(0) <= clk_pll_62m5;
rstlogic_clk_in(1) <= clk_pll_125m;
cmp_rstlogic_reset : gc_reset
generic map (
g_clocks => 2, -- 62.5MHz, 125MHz
g_logdelay => 4, -- 16 clock cycles
g_syncdepth => 3) -- length of sync chains
port map (
free_clk_i => clk_125m_pllref_buf,
locked_i => rstlogic_arst_n,
clks_i => rstlogic_clk_in,
rstn_o => rstlogic_rst_out);
-- distribution of resets (already synchronized to their clock domains)
rst_62m5_n <= rstlogic_rst_out(0);
rst_sys_62m5_n_o <= rst_62m5_n;
rst_ref_125m_n_o <= rstlogic_rst_out(1);
-----------------------------------------------------------------------------
-- Double-channel SPI DAC
-----------------------------------------------------------------------------
GEN_DAC_DEFAULT: if g_cute_version /= "2.1" generate
dac_val1_data <= dac_dpll_data;
dac_val1_load <= dac_dpll_load_p1;
dac_val2_data <= dac_hpll_data;
dac_val2_load <= dac_hpll_load_p1;
end generate;
GEN_DAC_CUTE_2_1: if g_cute_version = "2.1" generate
-- Cute 2.1 had hpll and dpll DACs swapped
dac_val1_data <= dac_hpll_data;
dac_val1_load <= dac_hpll_load_p1;
dac_val2_data <= dac_dpll_data;
dac_val2_load <= dac_dpll_load_p1;
end generate;
cmp_dac_arb: cute_serial_dac_arb
generic map (
g_invert_sclk => FALSE,
g_num_extra_bits => 8)
port map (
clk_i => clk_pll_62m5,
rst_n_i => rst_62m5_n,
val1_i => dac_val1_data,
load1_i => dac_val1_load,
val2_i => dac_val2_data,
load2_i => dac_val2_load,
dac_sync_n_o => plldac_sync_n_o,
dac_ldac_n_o => plldac_load_n_o,
dac_clr_n_o => plldac_clr_n_o,
dac_sclk_o => plldac_sclk_o,
dac_din_o => plldac_din_o);
-----------------------------------------------------------------------------
-- The WR PTP core with optional fabric interface attached
-----------------------------------------------------------------------------
cmp_board_common : xwrc_board_common
generic map (
g_simulation => g_simulation,
g_with_external_clock_input => g_with_external_clock_input,
g_board_name => "CUTE",
g_flash_secsz_kb => 64, -- sector size for M25P32
g_flash_sdbfs_baddr => 16#2e0000#, -- sdbfs after multiboot bitstream
g_phys_uart => TRUE,
g_virtual_uart => TRUE,
g_aux_clks => g_aux_clks,
g_ep_rxbuf_size => 1024,
g_tx_runt_padding => TRUE,
g_dpram_initf => g_dpram_initf,
g_dpram_size => 131072/4,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_aux_sdb => g_aux_sdb,
g_softpll_enable_debugger => FALSE,
g_vuart_fifo_size => 1024,
g_pcs_16bit => FALSE,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
g_diag_ro_size => g_diag_ro_size,
g_diag_rw_size => g_diag_rw_size,
g_streamers_op_mode => g_streamers_op_mode,
g_tx_streamer_params => g_tx_streamer_params,
g_rx_streamer_params => g_rx_streamer_params,
g_fabric_iface => g_fabric_iface
)
port map (
clk_sys_i => clk_pll_62m5,
clk_dmtd_i => clk_pll_dmtd,
clk_ref_i => clk_pll_125m,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext,
clk_ext_mul_i => ext_ref_mul,
clk_ext_mul_locked_i => ext_ref_mul_locked,
clk_ext_stopped_i => ext_ref_mul_stopped,
clk_ext_rst_o => ext_ref_rst,
pps_ext_i => pps_ext_i,
rst_n_i => rst_62m5_n,
dac_hpll_load_p1_o => dac_hpll_load_p1,
dac_hpll_data_o => dac_hpll_data,
dac_dpll_load_p1_o => dac_dpll_load_p1,
dac_dpll_data_o => dac_dpll_data,
phy8_o => phy8_from_wrc,
phy8_i => phy8_to_wrc,
scl_o => eeprom_scl_o,
scl_i => eeprom_scl_i,
sda_o => eeprom_sda_o,
sda_i => eeprom_sda_i,
sfp_scl_o => sfp_scl_out,
sfp_scl_i => sfp_scl_in,
sfp_sda_o => sfp_sda_out,
sfp_sda_i => sfp_sda_in,
sfp_det_i => sfp_det_in,
spi_sclk_o => flash_sclk_o,
spi_ncs_o => flash_ncs_o,
spi_mosi_o => flash_mosi_o,
spi_miso_i => flash_miso_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
owr_pwren_o => open,
owr_en_o => onewire_en,
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
aux_master_o => aux_master_out,
aux_master_i => aux_master_in,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
aux_diag_i => aux_diag_i,
aux_diag_o => aux_diag_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
timestamps_o => timestamps_o,
timestamps_ack_i => timestamps_ack_i,
abscal_txts_o => abscal_txts_o,
abscal_rxts_o => abscal_rxts_o,
fc_tx_pause_req_i => fc_tx_pause_req_i,
fc_tx_pause_delay_i => fc_tx_pause_delay_i,
fc_tx_pause_ready_o => fc_tx_pause_ready_o,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
led_act_o => led_act_o,
led_link_o => led_link_o,
btn1_i => btn1_i,
btn2_i => btn2_i,
pps_p_o => pps_p_o,
pps_csync_o => pps_csync,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o);
tm_time_valid_o <= tm_time_valid;
pps_csync_o <= pps_csync;
onewire_oen_o <= onewire_en(0);
onewire_in(0) <= onewire_i;
onewire_in(1) <= '1';
U_WRPC_MULTIBOOT: if (g_multiboot_enable = true) generate
multiboot_slave_in <= aux_master_out;
aux_master_in <= multiboot_slave_out;
aux_master_o <= cc_dummy_master_out;
cmp_clock_crossing: xwb_clock_crossing
port map (
slave_clk_i => clk_pll_62m5,
slave_rst_n_i => rst_62m5_n,
slave_i => multiboot_slave_in,
slave_o => multiboot_slave_out,
master_clk_i => clk_pll_20m,
master_rst_n_i => '1',
master_i => multiboot_wb_in,
master_o => multiboot_wb_out);
u_multiboot: xwb_xil_multiboot
port map (
clk_i => clk_pll_20m,
rst_n_i => '1',
wbs_i => multiboot_wb_out,
wbs_o => multiboot_wb_in,
spi_cs_n_o => open,
spi_sclk_o => open,
spi_mosi_o => open,
spi_miso_i => '0');
end generate;
U_WRPC_NO_MULTIBOOT: if (g_multiboot_enable = false) generate
aux_master_o <= aux_master_out;
aux_master_in <= aux_master_i;
end generate;
-----------------------------------------------------------------------------
-- 10MHz output generation
-----------------------------------------------------------------------------
aux_half_high <= to_unsigned(c_HALF, aux_half_high'length);
aux_half_low <= to_unsigned(c_HALF, aux_half_low'length);
aux_shift <= to_unsigned(11, aux_half_low'length);
rst_oserdes <= not pll_aux_locked;
clk_10m_ext_o <= sd_out(0);
process(clk_pll_125m)
begin
if rising_edge(clk_pll_125m) then
if(rstlogic_rst_out(1) = '0' or pll_aux_locked = '0') then
tm_time_valid_d1 <= '0';
elsif(pps_csync = '1') then
tm_time_valid_d1 <= tm_time_valid;
end if;
end if;
end process;
clk_realign <= (not tm_time_valid_d1) and tm_time_valid and pps_csync;
process(clk_pll_125m)
variable rest : integer range 0 to 65535;
variable v_bit : std_logic;
begin
if rising_edge(clk_pll_125m) then
if (rstlogic_rst_out(1)='0' or pll_aux_locked='0' or clk_realign='1') then
rest := to_integer(aux_half_high - aux_shift);
v_bit := '1';
else
for i in 0 to c_DATA_W-1 loop
if(rest /= 0) then
sd_data(i) <= v_bit;
rest := rest - 1;
elsif(v_bit = '1') then
sd_data(i) <= '0';
v_bit := '0';
rest := to_integer(aux_half_low-1); -- because here we already wrote first bit
-- from this group
elsif(v_bit = '0') then
sd_data(i) <= '1';
v_bit := '1';
rest := to_integer(aux_half_high-1);
end if;
end loop;
end if;
end if;
end process;
U_10MHZ_SERDES: oserdes_4_to_1
generic map(
dev_w => c_DATA_W)
port map(
data_out_from_device => sd_data,
data_out_to_pins => sd_out,
delay_reset => '0',
clk_in => clk_pll_aux_out(0), --500MHz
pll_locked => pll_aux_locked,
clk_div_in => clk_pll_125m,
io_reset => rst_oserdes);
end architecture struct;
modules/timing/Manifest.py
View file @ f1b7521d
......@@ -3,5 +3,6 @@ files = ["dmtd_phase_meas.vhd",
"multi_dmtd_with_deglitcher.vhd",
"hpll_period_detect.vhd",
"pulse_gen.vhd",
"oserdes_4_to_1.vhd",
"pulse_stamper.vhd" ]
modules/timing/oserdes_4_to_1.vhd 0 → 100644
View file @ f1b7521d
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity oserdes_4_to_1 is
generic
(-- width of the data for the system
sys_w : integer := 1;
-- width of the data for the device
dev_w : integer := 4);
port
(
-- from the device out to the system
data_out_from_device : in std_logic_vector(dev_w-1 downto 0);
data_out_to_pins : out std_logic_vector(sys_w-1 downto 0);
-- input, output delay control signals
delay_reset : in std_logic; -- active high synchronous reset for input delay
-- clock and reset signals
clk_in : in std_logic;
pll_locked : in std_logic;
clk_div_in : in std_logic;
io_reset : in std_logic); -- reset signal for io circuit
end oserdes_4_to_1;
architecture xilinx of oserdes_4_to_1 is
constant num_serial_bits : integer := dev_w/sys_w;
signal ioclk : std_logic;
type serdarr is array (0 to 3) of std_logic_vector(sys_w-1 downto 0);
-- array to use intermediately from the serdes to the internal
-- devices. bus "0" is the leftmost bus
-- * fills in from higher order
signal oserdes_d : serdarr := (( others => (others => '0')));
signal serdesstrobe : std_logic;
-- delay ctrl
signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
signal data_delay : std_logic_vector(sys_w-1 downto 0);
type loadarr is array (0 to 15) of std_logic_vector(4 downto 0);
signal intap : loadarr := (( others => (others => '0')));
signal outtap : loadarr := (( others => (others => '0')));
begin
bufpll_inst : bufpll
generic map (
divide => 4, -- divclk divider (1-8)
enable_sync => true -- enable synchrnonization between pll and gclk (true/false)
)
port map (
ioclk => ioclk, -- 1-bit output: output i/o clock
lock => open, -- 1-bit output: synchronized lock output
serdesstrobe => serdesstrobe, -- 1-bit output: output serdes strobe (connect to iserdes2/oserdes2)
gclk => clk_div_in, -- 1-bit input: bufg clock input
locked => pll_locked, -- 1-bit input: locked input from pll
pllin => clk_in -- 1-bit input: clock input from pll
);
-- we have multiple bits- step over every bit, instantiating the required elements
pins: for pin_count in 0 to sys_w-1 generate
begin
data_out_to_pins(pin_count) <= data_delay(pin_count);
iodelay2_inst : iodelay2
generic map (
counter_wraparound => "wraparound", -- "stay_at_limit" or "wraparound"
data_rate => "sdr", -- "sdr" or "ddr"
delay_src => "odatain", -- "io", "odatain" or "idatain"
idelay2_value => 0, -- delay value when idelay_mode="pci" (0-255)
idelay_mode => "normal", -- "normal" or "pci"
idelay_type => "default", -- "fixed", "default", "variable_from_zero", "variable_from_half_max"
-- or "diff_phase_detector"
idelay_value => 0, -- amount of taps for fixed input delay (0-255)
odelay_value => 33, -- amount of taps fixed output delay (0-255)
serdes_mode => "none", -- "none", "master" or "slave"
sim_tapdelay_value => 75 -- per tap delay used for simulation in ps
)
port map (
busy => open, -- 1-bit output: busy output after cal
dataout => open, -- 1-bit output: delayed data output to iserdes/input register
dataout2 => open, -- 1-bit output: delayed data output to general fpga fabric
dout => data_delay(pin_count), -- 1-bit output: delayed data output
tout => open, -- 1-bit output: delayed 3-state output
cal => '0', -- 1-bit input: initiate calibration input
ce => '0', -- 1-bit input: enable inc input
clk => clk_div_in, -- 1-bit input: clock input
idatain => '0', -- 1-bit input: data input (connect to top-level port or i/o buffer)
inc => '0', -- 1-bit input: increment / decrement input
ioclk0 => ioclk, -- 1-bit input: input from the i/o clock network
ioclk1 => '0', -- 1-bit input: input from the i/o clock network
odatain => data_out_to_pins_predelay(pin_count), -- 1-bit input: output data input from output register or oserdes2.
rst => delay_reset, -- 1-bit input: reset to zero or 1/2 of total delay period
t => '0' -- 1-bit input: 3-state input signal
);
-- instantiate the serdes primitive
-- declare the oserdes
oserdes2_inst : oserdes2
generic map (
bypass_gclk_ff => false, -- bypass clkdiv syncronization registers (true/false)
data_rate_oq => "sdr", -- output data rate ("sdr" or "ddr")
data_rate_ot => "sdr", -- 3-state data rate ("sdr" or "ddr")
data_width => 4, -- parallel data width (2-8)
output_mode => "single_ended", -- "single_ended" or "differential"
serdes_mode => "none", -- "none", "master" or "slave"
train_pattern => 0 -- training pattern (0-15)
)
port map (
oq => data_out_to_pins_predelay(pin_count), -- 1-bit output: data output to pad or iodelay2
shiftout1 => open, -- 1-bit output: cascade data output
shiftout2 => open, -- 1-bit output: cascade 3-state output
shiftout3 => open, -- 1-bit output: cascade differential data output
shiftout4 => open, -- 1-bit output: cascade differential 3-state output
tq => open, -- 1-bit output: 3-state output to pad or iodelay2
clk0 => ioclk, -- 1-bit input: i/o clock input
clk1 => '0', -- 1-bit input: secondary i/o clock input
clkdiv => clk_div_in, -- 1-bit input: logic domain clock input
-- d1 - d4: 1-bit (each) input: parallel data inputs
d1 => oserdes_d(3)(pin_count),
d2 => oserdes_d(2)(pin_count),
d3 => oserdes_d(1)(pin_count),
d4 => oserdes_d(0)(pin_count),
ioce => serdesstrobe, -- 1-bit input: data strobe input
oce => '1', -- 1-bit input: clock enable input
rst => io_reset, -- 1-bit input: asynchrnous reset input
shiftin1 => '1', -- 1-bit input: cascade data input
shiftin2 => '1', -- 1-bit input: cascade 3-state input
shiftin3 => '1', -- 1-bit input: cascade differential data input
shiftin4 => '1', -- 1-bit input: cascade differential 3-state input
-- t1 - t4: 1-bit (each) input: 3-state control inputs
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0', -- 1-bit input: 3-state clock enable input
train => '0' -- 1-bit input: training pattern enable input
);
out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- this places the first data in time on the right
oserdes_d(4-slice_count-1)(pin_count) <=
data_out_from_device(slice_count);
-- to place the first data in time on the left, use the
-- following code, instead
-- oserdes_d(slice_count) <=
-- data_out_from_device(slice_count);
end generate out_slices;
end generate pins;
end xilinx;
modules/wr_dacs/Manifest.py
View file @ f1b7521d
files = [
"spec_serial_dac_arb.vhd",
"spec_serial_dac.vhd"
"spec_serial_dac.vhd",
"cute_serial_dac_arb.vhd",
"cute_serial_dac.vhd"
]
modules/wr_dacs/cute_serial_dac.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : Serial DAC interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : serial_dac.vhd
-- Author : paas, slayer
-- Company : CERN BE-Co-HT
-- Created : 2010-02-25
-- Last update: 2011-05-10
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: The dac unit provides an interface to a 16 bit serial Digita to
-- Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :1
-- Date Version Author Description
-- 2009-01-24 1.0 paas Created
-- 2010-02-25 1.1 slayer Modified for rev 1.1 switch
-- 2012-10-15 2.0 pwb Modified for AD5663R of CUTE-WR
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cute_serial_dac is
generic (
g_num_data_bits : integer := 16;
g_num_extra_bits : integer := 8
);
port (
-- clock & reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- channel 1 value and value load strobe
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
load_i : in std_logic;
-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
sclk_divsel_i : in std_logic_vector(2 downto 0);
-- DAC I/F
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic
);
end cute_serial_dac;
architecture syn of cute_serial_dac is
signal divider : unsigned(11 downto 0);
signal dataSh : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
signal bitCounter : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
signal endSendingData : std_logic;
signal sendingData : std_logic;
signal iDacClk : std_logic;
signal iValidValue : std_logic;
signal divider_muxed : std_logic;
begin
-- Modified by Weibin
select_divider : process (divider, sclk_divsel_i)
begin -- process
case sclk_divsel_i is
when "000" => divider_muxed <= divider(2); -- sclk = clk_i/8
when "001" => divider_muxed <= divider(3); -- sclk = clk_i/16
when "010" => divider_muxed <= divider(4); -- sclk = clk_i/32
when "011" => divider_muxed <= divider(5); -- sclk = clk_i/64
when "100" => divider_muxed <= divider(6); -- sclk = clk_i/128
when "101" => divider_muxed <= divider(7); -- sclk = clk_i/256
when "110" => divider_muxed <= divider(8); -- sclk = clk_i/512
when "111" => divider_muxed <= divider(9); -- sclk = clk_i/1024
when others => null;
end case;
end process;
iValidValue <= load_i;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
sendingData <= '0';
else
if iValidValue = '1' and sendingData = '0' then
sendingData <= '1';
elsif endSendingData = '1' then
sendingData <= '0';
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' then
divider <= (divider'high downto 1 => '0') & '1';
elsif sendingData = '1' then
if(divider_muxed = '1') then
divider <= (divider'high downto 1 => '0') & '1';
else
divider <= divider + 1;
end if;
elsif endSendingData = '1' then
divider <= (divider'high downto 1 => '0') & '1';
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
iDacClk <= '1'; -- 0
else
if iValidValue = '1' then
iDacClk <= '1'; -- 0
elsif divider_muxed = '1' then
iDacClk <= not(iDacClk);
elsif endSendingData = '1' then
iDacClk <= '1'; -- 0
end if;
end if;
end if;
end process;
process(clk_i, rst_n_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dataSh <= (others => '0');
else
if iValidValue = '1' and sendingData = '0' then
dataSh(g_num_data_bits-1 downto 0) <= value_i;
dataSh(dataSh'left downto g_num_data_bits) <= cmd_i;
elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
dataSh(0) <= dataSh(dataSh'left);
dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if iValidValue = '1' and sendingData = '0' then
bitCounter(0) <= '1';
bitCounter(bitCounter'left downto 1) <= (others => '0');
elsif sendingData = '1' and to_integer(divider) = 1 and iDacClk = '1' then
bitCounter(0) <= '0';
bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
end if;
end if;
end process;
endSendingData <= bitCounter(bitCounter'left);
xdone_o <= not SendingData;
dac_sdata_o <= dataSh(dataSh'left);
dac_sync_n_o <= not sendingData;
dac_sclk_o <= iDacClk;
end syn;
modules/wr_dacs/cute_serial_dac_arb.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : CUTE serial DAC interface with arbiter
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : cute_serial_dac.vhd
-- Author : Pan Weibin
-- Company : Tsinghua Univ.
-- Platform : fpga-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
--
-- Copyright (c) 2018 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cute_serial_dac_arb is
generic(
g_invert_sclk : boolean;
g_num_extra_bits : integer
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
val1_i : in std_logic_vector(15 downto 0);
load1_i : in std_logic;
val2_i : in std_logic_vector(15 downto 0);
load2_i : in std_logic;
dac_ldac_n_o : out std_logic;
dac_clr_n_o : out std_logic;
dac_sync_n_o : out std_logic;
dac_sclk_o : out std_logic;
dac_din_o : out std_logic);
end cute_serial_dac_arb;
architecture behavioral of cute_serial_dac_arb is
component cute_serial_dac
generic (
g_num_data_bits : integer;
g_num_extra_bits : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
value_i : in std_logic_vector(g_num_data_bits-1 downto 0);
cmd_i : in std_logic_vector(g_num_extra_bits-1 downto 0);
load_i : in std_logic;
sclk_divsel_i : in std_logic_vector(2 downto 0);
dac_sclk_o : out std_logic;
dac_sdata_o : out std_logic;
dac_sync_n_o : out std_logic;
xdone_o : out std_logic);
end component;
signal d1, d2 : std_logic_vector(15 downto 0);
signal d1_ready, d2_ready : std_logic;
signal dac_data : std_logic_vector(15 downto 0);
signal dac_load : std_logic;
signal dac_cs_sel : std_logic_vector(1 downto 0);
signal dac_done : std_logic;
signal dac_sclk_int : std_logic;
signal dac_cmd : std_logic_vector(g_num_extra_bits-1 downto 0);
signal init_cnt : unsigned(7 downto 0);
type t_state is (INIT, ENABLE_INT_REF, WAIT_DONE, LOAD_DAC, WAIT_DATA);
signal state : t_state;
signal trig0 : std_logic_vector(31 downto 0);
signal trig1 : std_logic_vector(31 downto 0);
signal trig2 : std_logic_vector(31 downto 0);
signal trig3 : std_logic_vector(31 downto 0);
signal CONTROL0 : std_logic_vector(35 downto 0);
begin -- behavioral
dac_clr_n_o <= '1';
dac_ldac_n_o <= '0';
U_DAC : cute_serial_dac
generic map (
g_num_data_bits => 16,
g_num_extra_bits => g_num_extra_bits)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
value_i => dac_data,
cmd_i => dac_cmd,
load_i => dac_load,
sclk_divsel_i => "001",
dac_sclk_o => dac_sclk_int,
dac_sdata_o => dac_din_o,
dac_sync_n_o => dac_sync_n_o,
xdone_o => dac_done);
p_drive_sclk: process(dac_sclk_int)
begin
if(g_invert_sclk) then
dac_sclk_o <= not dac_sclk_int;
else
dac_sclk_o <= dac_sclk_int;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
d1 <= (others => '0');
d1_ready <= '0';
d2 <= (others => '0');
d2_ready <= '0';
dac_load <= '0';
init_cnt <= (others => '0');
state <= INIT;
else
if(load1_i = '1' or load2_i = '1') then
if(load1_i = '1') then
d1_ready <= '1';
d1 <= val1_i;
end if;
if(load2_i = '1') then
d2_ready <= '1';
d2 <= val2_i;
end if;
else
case state is
when INIT =>
if init_cnt(6) = '1' then
state <= ENABLE_INT_REF;
else
init_cnt <= init_cnt +1;
end if;
when ENABLE_INT_REF =>
dac_cmd <= "00111000";
dac_data <= (dac_data'high downto 1 => '0') & '0'; -- internal reference setup
dac_load <= '1';
state <= LOAD_DAC;
when WAIT_DATA =>
if(d1_ready = '1') then
dac_data <= d1;
dac_cmd <= "00011001"; -- write and update DAC B
dac_load <= '1';
d1_ready <= '0';
state <= LOAD_DAC;
elsif(d2_ready = '1') then
dac_data <= d2;
dac_cmd <= "00011000"; -- write and update DAC A
dac_load <= '1';
d2_ready <= '0';
state <= LOAD_DAC;
end if;
when LOAD_DAC=>
dac_load <= '0';
state <= WAIT_DONE;
when WAIT_DONE =>
if(dac_done = '1') then
state <= WAIT_DATA;
end if;
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd
View file @ f1b7521d
......@@ -37,6 +37,8 @@ entity WHITERABBITGTP_WRAPPER_TILE_SPARTAN6 is
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
REFSELDYPLL0 : in std_logic_vector(2 downto 0):=(others=>'0');
REFSELDYPLL1 : in std_logic_vector(2 downto 0):=(others=>'0');
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
......@@ -483,8 +485,8 @@ begin
REFCLKPLL1 => open,
REFCLKPWRDNB0 => tied_to_vcc_i,
REFCLKPWRDNB1 => tied_to_vcc_i,
REFSELDYPLL0 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL1 => tied_to_ground_vec_i(2 downto 0),
REFSELDYPLL0 => REFSELDYPLL0,
REFSELDYPLL1 => REFSELDYPLL1,
RESETDONE0 => RESETDONE0_OUT,
RESETDONE1 => RESETDONE1_OUT,
TSTCLK0 => tied_to_ground_i,
......
platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd
View file @ f1b7521d
......@@ -66,7 +66,7 @@ entity wr_gtp_phy_spartan6 is
-- Port 0
-- dedicated GTP clock input
gtp_clk_i : in std_logic;
gtp0_clk_i : in std_logic;
-- TX path, synchronous to ch0_ref_clk_i
ch0_ref_clk_i : in std_logic;
......@@ -118,6 +118,9 @@ entity wr_gtp_phy_spartan6 is
ch0_rdy_o : out std_logic;
-- Port 1
-- dedicated GTP clock input
gtp1_clk_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -137,6 +140,10 @@ entity wr_gtp_phy_spartan6 is
ch1_tx_prbs_sel_i: in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
-- PLL source
ch0_ref_sel_pll : in std_logic_vector(2 downto 0);
ch1_ref_sel_pll : in std_logic_vector(2 downto 0);
-- Serial I/O
pad_txn0_o : out std_logic;
......@@ -183,6 +190,8 @@ architecture rtl of wr_gtp_phy_spartan6 is
PLLLKDET1_OUT : out std_logic;
RESETDONE0_OUT : out std_logic;
RESETDONE1_OUT : out std_logic;
REFSELDYPLL0 : in std_logic_vector(2 downto 0):=(others=>'0');
REFSELDYPLL1 : in std_logic_vector(2 downto 0):=(others=>'0');
RXCHARISK0_OUT : out std_logic;
RXCHARISK1_OUT : out std_logic;
RXDISPERR0_OUT : out std_logic;
......@@ -387,8 +396,8 @@ begin -- rtl
ch0_gtp_reset <= ch0_rst_synced or std_logic(not ch0_reset_counter(ch0_reset_counter'left));
ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
ch0_ref_clk_in(0) <= gtp_clk_i;
ch0_ref_clk_in(1) <= '0';
ch0_ref_clk_in(0) <= gtp0_clk_i;
ch0_ref_clk_in(1) <= gtp1_clk_i;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch0_gtp_loopback <= "010" when(ch0_loopen_i = '1') else
ch0_loopen_vec_i;
......@@ -554,8 +563,8 @@ begin -- rtl
ch1_gtp_reset <= ch1_rst_synced or std_logic(not ch1_reset_counter(ch1_reset_counter'left));
ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
ch1_ref_clk_in(0) <= gtp_clk_i;
ch1_ref_clk_in(1) <= '0';
ch1_ref_clk_in(0) <= gtp0_clk_i;
ch1_ref_clk_in(1) <= gtp1_clk_i;
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch1_gtp_loopback <= "010" when(ch1_loopen_i = '1') else
ch1_loopen_vec_i;
......@@ -740,7 +749,8 @@ begin -- rtl
PLLLKDET1_OUT => ch1_gtp_pll_lockdet,
RESETDONE0_OUT => ch0_gtp_reset_done,
RESETDONE1_OUT => ch1_gtp_reset_done,
REFSELDYPLL0 => ch0_ref_sel_pll,
REFSELDYPLL1 => ch1_ref_sel_pll,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISK0_OUT => ch0_rx_k_int,
RXCHARISK1_OUT => ch1_rx_k_int,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ f1b7521d
......@@ -41,11 +41,12 @@ package wr_xilinx_pkg is
-- Configuration of used-defined aux PLL clocks
type t_auxpll_cfg is record
enabled : boolean;
bufg_en : boolean;
divide : integer;
end record t_auxpll_cfg;
type t_auxpll_cfg_array is array (0 to 3) of t_auxpll_cfg;
constant c_AUXPLL_CFG_DEFAULT : t_auxpll_cfg := (FALSE, 1);
constant c_AUXPLL_CFG_DEFAULT : t_auxpll_cfg := (FALSE, FALSE, 1);
constant c_AUXPLL_CFG_ARRAY_DEFAULT : t_auxpll_cfg_array := (others=>c_AUXPLL_CFG_DEFAULT);
component xwrc_platform_xilinx is
......@@ -57,6 +58,7 @@ package wr_xilinx_pkg is
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
g_phy_refclk_sel : integer range 0 to 7 := 0;
g_simulation : integer := 0
);
port (
......@@ -96,6 +98,7 @@ package wr_xilinx_pkg is
pll_aux_locked_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......@@ -116,7 +119,7 @@ package wr_xilinx_pkg is
g_enable_ch1 : integer := 1;
g_simulation : integer := 0);
port (
gtp_clk_i : in std_logic;
gtp0_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic := '0';
ch0_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch0_tx_k_i : in std_logic := '0';
......@@ -132,6 +135,7 @@ package wr_xilinx_pkg is
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch0_rdy_o : out std_logic;
gtp1_clk_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
......@@ -147,6 +151,8 @@ package wr_xilinx_pkg is
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_tx_prbs_sel_i : in std_logic_vector(2 downto 0) := (others => '0');
ch1_rdy_o : out std_logic;
ch0_ref_sel_pll : in std_logic_vector(2 downto 0) := (others => '0');
ch1_ref_sel_pll : in std_logic_vector(2 downto 0) := (others => '0');
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ f1b7521d
......@@ -41,6 +41,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.endpoint_pkg.all;
......@@ -65,6 +66,8 @@ entity xwrc_platform_xilinx is
-- Select GTP channel to use
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
-- Select PHY reference clock
g_phy_refclk_sel : integer range 0 to 7 := 0;
g_gtp_mux_enable : boolean := FALSE;
-- Set to TRUE will speed up some initialization processes
g_simulation : integer := 0);
......@@ -147,6 +150,7 @@ entity xwrc_platform_xilinx is
-- PLL outputs
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_20m_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
pll_locked_o : out std_logic;
......@@ -235,6 +239,7 @@ begin -- architecture rtl
-- 125MHz reference clock
gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
signal clk_20m : std_logic;
signal clk_sys : std_logic;
signal clk_sys_out : std_logic;
signal clk_sys_fb : std_logic;
......@@ -262,13 +267,14 @@ begin -- architecture rtl
CLKOUT0_DIVIDE => 16,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8,
-- 1st aux user clock parameters
CLKOUT1_DIVIDE => g_aux_pll_cfg(0).divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
-- Aux user clocks parameters
CLKOUT2_DIVIDE => g_aux_pll_cfg(0).divide,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
-- The rest of aux user clocks parameters
CLKOUT3_DIVIDE => g_aux_pll_cfg(1).divide,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
......@@ -284,8 +290,10 @@ begin -- architecture rtl
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
CLKOUT1 => clk_125m_pllref_buf_int2,
CLKOUT2 => clk_pll_aux(0),
CLKOUT1 => clk_pll_aux(0), -- required for 500MHz generation for
-- Cute-WR. This is because 500MHz goes then to BUFPLL which can input
-- only CLKOUT0/1 from PLL_BASE.
CLKOUT2 => clk_125m_pllref_buf_int2,
CLKOUT3 => clk_pll_aux(1),
CLKOUT4 => clk_pll_aux(2),
CLKOUT5 => clk_pll_aux(3),
......@@ -300,14 +308,20 @@ begin -- architecture rtl
O => clk_125m_pllref_buf_int1,
I => clk_125m_pllref_i);
-- DDR PLL global clock buffers
-- PLL aux clocks buffers
gen_auxclk_bufs: for I in 0 to 3 generate
gen_auxclk_enabled: if g_aux_pll_cfg(I).enabled = TRUE generate
-- Aux PLL_BASE clocks with BUFG enabled
gen_auxclk_bufg_en: if g_aux_pll_cfg(I).enabled = TRUE and g_aux_pll_cfg(I).bufg_en = TRUE generate
cmp_auxclk_bufg : BUFG
port map (
O => clk_pll_aux_o(I),
I => clk_pll_aux(I));
end generate;
-- Aux PLL_BASE clocks with BUFG disabled
gen_auxclk_no_bufg: if g_aux_pll_cfg(I).enabled = TRUE and g_aux_pll_cfg(I).bufg_en = FALSE generate
clk_pll_aux_o(I) <= clk_pll_aux(I);
end generate;
-- Disabled aux PLL_BASE clocks
gen_auxclk_disabled: if g_aux_pll_cfg(I).enabled = FALSE generate
clk_pll_aux_o(I) <= '0';
end generate;
......@@ -325,6 +339,7 @@ begin -- architecture rtl
O => clk_125m_pllref_buf,
I => clk_125m_pllref_buf_int2);
clk_20m_o <= clk_20m_vcxo_buf;
clk_62m5_sys_o <= clk_sys_out;
clk_125m_ref_o <= clk_125m_pllref_buf;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
......@@ -1031,7 +1046,9 @@ begin -- architecture rtl
gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
signal clk_125m_gtp_buf : std_logic;
signal clk_125m_gtp_buf : std_logic;
signal clk_125m_gtp1_buf : std_logic;
signal clk_125m_gtp0_buf : std_logic;
signal ch0_phy8_out, ch1_phy8_out : t_phy_8bits_to_wrc;
......@@ -1059,7 +1076,7 @@ begin -- architecture rtl
g_enable_ch0 => g_gtp_enable_ch0,
g_enable_ch1 => g_gtp_enable_ch1)
port map (
gtp_clk_i => clk_125m_gtp_buf,
gtp0_clk_i => clk_125m_gtp0_buf,
ch0_ref_clk_i => clk_125m_pllref_buf,
ch0_tx_data_i => phy8_i.tx_data,
ch0_tx_k_i => phy8_i.tx_k(0),
......@@ -1075,6 +1092,8 @@ begin -- architecture rtl
ch0_loopen_vec_i => phy8_i.loopen_vec,
ch0_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
ch0_rdy_o => ch0_phy8_out.rdy,
ch0_ref_sel_pll => std_logic_vector(to_unsigned(g_phy_refclk_sel, 3)),
gtp1_clk_i => clk_125m_gtp1_buf,
ch1_ref_clk_i => clk_125m_pllref_buf,
ch1_tx_data_i => phy8_i.tx_data,
ch1_tx_k_i => phy8_i.tx_k(0),
......@@ -1090,6 +1109,7 @@ begin -- architecture rtl
ch1_loopen_vec_i => phy8_i.loopen_vec,
ch1_tx_prbs_sel_i => phy8_i.tx_prbs_sel,
ch1_rdy_o => ch1_phy8_out.rdy,
ch1_ref_sel_pll => std_logic_vector(to_unsigned(g_phy_refclk_sel, 3)),
pad_txn0_o => ch0_sfp_txn,
pad_txp0_o => ch0_sfp_txp,
pad_rxn0_i => ch0_sfp_rxn,
......@@ -1101,6 +1121,8 @@ begin -- architecture rtl
);
gen_gtp_ch0 : if (g_gtp_enable_ch0 = 1 and g_gtp_enable_ch1 = 0) generate
clk_125m_gtp0_buf <= clk_125m_gtp_buf;
clk_125m_gtp1_buf <= '0';
ch0_phy8_out.ref_clk <= clk_125m_pllref_buf;
ch0_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
ch0_phy8_out.sfp_los <= sfp_los_i;
......@@ -1112,6 +1134,8 @@ begin -- architecture rtl
end generate gen_gtp_ch0;
gen_gtp_ch1 : if (g_gtp_enable_ch0 = 0 and g_gtp_enable_ch1 = 1) generate
clk_125m_gtp0_buf <= '0';
clk_125m_gtp1_buf <= clk_125m_gtp_buf;
ch1_phy8_out.ref_clk <= clk_125m_pllref_buf;
ch1_phy8_out.sfp_tx_fault <= sfp_tx_fault_i;
ch1_phy8_out.sfp_los <= sfp_los_i;
......
syn/cute_core_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "csg324"
syn_top = "cute_core_ref_top"
syn_project = "cute_core_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/cute_ref_design/"}
syn/cute_core_ref_design/README 0 → 100644
View file @ f1b7521d
As there are thousands of nodes in LHAASO project, we merge the WR function with
user module into one FPGA. So they just need the cute_core. The
syn/cute_core_ref is used to generate the ngc for them.
syn/cute_ref_design/Makefile 0 → 100644
View file @ f1b7521d
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := cute_wr_ref.xise
ISE_CRAP := *.b cute_wr_ref_top_summary.html *.tcl cute_wr_ref_top.bld cute_wr_ref_top.cmd_log *.drc cute_wr_ref_top.lso *.ncd cute_wr_ref_top.ngc cute_wr_ref_top.ngd cute_wr_ref_top.ngr cute_wr_ref_top.pad cute_wr_ref_top.par cute_wr_ref_top.pcf cute_wr_ref_top.prj cute_wr_ref_top.ptwx cute_wr_ref_top.stx cute_wr_ref_top.syr cute_wr_ref_top.twr cute_wr_ref_top.twx cute_wr_ref_top.gise $(PROJECT).gise cute_wr_ref_top.bgn cute_wr_ref_top.unroutes cute_wr_ref_top.ut cute_wr_ref_top.xpi cute_wr_ref_top.xst cute_wr_ref_top_bitgen.xwbt cute_wr_ref_top_envsettings.html cute_wr_ref_top_guide.ncd cute_wr_ref_top_map.map cute_wr_ref_top_map.mrp cute_wr_ref_top_map.ncd cute_wr_ref_top_map.ngm cute_wr_ref_top_map.xrpt cute_wr_ref_top_ngdbuild.xrpt cute_wr_ref_top_pad.csv cute_wr_ref_top_pad.txt cute_wr_ref_top_par.xrpt cute_wr_ref_top_summary.xml cute_wr_ref_top_usage.xml cute_wr_ref_top_xst.xrpt usage_statistics_webtalk.html par_usage_statistics.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local: syn_pre_cmd check_tool generate_tcl synthesis syn_post_cmd
generate_tcl:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Synthesize - XST}" >> run.tcl
echo "process run {Translate}" >> run.tcl
echo "process run {Map}" >> run.tcl
echo "process run {Place & Route}" >> run.tcl
echo "process run {Generate Programming File}" >> run.tcl
synthesis:
/home/greg/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/xtclsh run.tcl
check_tool:
syn_post_cmd:
syn_pre_cmd:
#target for cleaning all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
.PHONY: mrproper clean syn_pre_cmd syn_post_cmd synthesis local check_tool
USER:=$(HDLMAKE_RSYNTH_USER)# take the value from the environment
SERVER:=$(HDLMAKE_RSYNTH_SERVER)# take the value from the environment
ISE_PATH:=$(HDLMAKE_RSYNTH_ISE_PATH)
R_NAME:=greg/cute_wr_ref
PORT:=22
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile or setting env. variable HDLMAKE_RSYNTH_USER." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile or setting env. variable HDLMAKE_RSYNTH_SERVER." && false
endif
ifeq (x$(ISE_PATH),x)
@echo "Remote synthesis server is not set. You can set it by editing variable ISE_PATH in the makefile or setting env. variable HDLMAKE_RSYNTH_ISE_PATH." && false
endif
CWD := $(shell pwd)
FILES := ../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_commit_fifo.vhd \
../../top/cute_ref_design/cute_wr_ref_top.ucf \
../../modules/wr_si57x_interface/xwr_si57x_interface.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_wbm_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_user_csr.vhd \
../../modules/wr_endpoint/ep_sync_detect.vhd \
../../modules/wr_pps_gen/wr_pps_gen.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_top.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_slave_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../modules/fabric/xwrf_loopback/wrf_loopback.vhd \
../../modules/wr_endpoint/ep_tx_inject_ctrl.vhd \
../../modules/wr_endpoint/ep_wishbone_controller.vhd \
../../modules/wr_endpoint/endpoint_pkg.vhd \
../../modules/wr_tbi_phy/enc_8b10b.vhd \
../../modules/wrc_core/wrc_syscon_pkg.vhd \
../../modules/wr_eca/eca_tlu_fsm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_wb_if.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd \
../../platform/xilinx/chipscope/chipscope_icon.ngc \
../../platform/xilinx/wr_gtp_phy/spartan6/whiterabbitgtp_wrapper_tile_spartan6.vhd \
../../modules/wr_eca/eca_free.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../modules/wr_endpoint/ep_rtu_header_extract.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd \
../../modules/wr_endpoint/ep_tx_path.vhd \
../../modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd \
../../modules/wr_endpoint/ep_tx_pcs_16bit.vhd \
../../modules/wrc_core/wrc_periph.vhd \
../../modules/wr_eca/eca_pkg.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_irq_controller.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../modules/wr_softpll_ng/spll_aligner.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../modules/wr_endpoint/ep_rx_oob_insert.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../modules/wr_eca/eca_msi.vhd \
../../modules/wrc_core/wr_core.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../modules/timing/multi_dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../modules/wr_mini_nic/xwr_mini_nic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../modules/wr_endpoint/ep_tx_header_processor.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../modules/wr_eca/eca_channel.vhd \
../../modules/wr_eca/wr_eca.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../modules/wr_eca/eca_offset.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../modules/wr_endpoint/ep_crc32_pkg.vhd \
../../modules/wr_endpoint/ep_rx_pcs_8bit.vhd \
../../modules/wr_softpll_ng/spll_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../modules/wr_eca/eca_wb_event.vhd \
../../modules/wr_tlu/tlu_fsm.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme64x_pkg.vhd \
../../modules/fabric/xwrf_loopback/lbk_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../modules/wr_dacs/spec_serial_dac_arb.vhd \
../../modules/wr_streamers/xrx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd \
../../modules/wr_eca/eca_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../modules/wr_endpoint/ep_rx_crc_size_check.vhd \
../../platform/xilinx/wr_gtp_phy/spartan6/wr_gtp_phy_spartan6.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../modules/wr_tlu/tlu_pkg.vhd \
../../board/cute/wr_cute_pkg.vhd \
../../modules/wr_dacs/cute_serial_dac.vhd \
../../modules/wr_eca/eca_ac_wbm_auto.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd \
../../modules/wr_softpll_ng/xwr_softpll_ng.vhd \
../../modules/wr_eca/eca_tlu.vhd \
cute_wr_ref.xise \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_usb_core/ez_usb_fifos.vhd \
../../modules/wr_mini_nic/minic_wb_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../platform/xilinx/wr_xilinx_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../modules/fabric/wr_fabric_pkg.vhd \
../../modules/wr_eca/eca_sdp.vhd \
../../modules/wr_eca/eca_scan.vhd \
../../modules/wr_streamers/xrtx_streamers_stats.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../modules/wr_endpoint/ep_rx_path.vhd \
../../modules/wr_streamers/dropping_buffer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../modules/fabric/xwrf_reg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../../modules/wr_eca/eca_ac_wbm_auto_pkg.vhd \
../../modules/timing/dmtd_phase_meas.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd \
../../modules/wr_endpoint/ep_rx_pcs_16bit.vhd \
run.tcl \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../modules/wr_eca/eca_scubus_channel.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd \
../../board/cute/xwrc_board_cute.vhd \
../../modules/timing/pulse_stamper.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../modules/wr_streamers/streamers_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd \
../../modules/wr_streamers/rx_streamer.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../modules/timing/dmtd_with_deglitcher.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../platform/xilinx/xwrc_platform_xilinx.vhd \
../../modules/wr_endpoint/ep_timestamping_unit.vhd \
../../modules/fabric/xwb_fabric_sink.vhd \
../../modules/wrc_core/wrc_diags_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../modules/wr_si57x_interface/si570_if_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../../modules/wr_endpoint/ep_rx_wb_master.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_bus.vhd \
../../modules/wrc_core/wrcore_pkg.vhd \
../../modules/wr_endpoint/ep_sync_detect_16bit.vhd \
../../modules/wr_eca/eca_adder.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../modules/fabric/xwrf_mux.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../modules/wrc_core/xwrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd \
../../modules/wr_tlu/tlu.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../top/cute_ref_design/cute_wr_ref_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../modules/wr_eca/eca_piso_fifo.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd \
../../modules/wrc_core/wrc_syscon_wb.vhd \
../../modules/wrc_core/xwr_core.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_cfg_fifo.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../modules/wr_eca/eca_rmw.vhd \
../../modules/wr_endpoint/ep_tx_pcs_8bit.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme64x_core.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/wb_skidpad.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../../platform/xilinx/wr_gtp_phy/spartan6/gtp_phase_align.vhd \
../../modules/wr_endpoint/ep_tx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_raw_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../modules/wr_dacs/spec_serial_dac.vhd \
../../modules/wrc_core/wrc_diags_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../modules/wr_pps_gen/xwr_pps_gen.vhd \
../../board/common/xwrc_board_common.vhd \
../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc \
../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../modules/fabric/xwb_fabric_source.vhd \
../../modules/wr_eca/eca_tlu_auto.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../modules/wr_eca/eca_tlu_auto_pkg.vhd \
../../modules/wr_tbi_phy/wr_tbi_phy.vhd \
../../platform/xilinx/chipscope/chipscope_ila.ngc \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../modules/wr_streamers/xwr_streamers.vhd \
../../modules/wr_softpll_ng/spll_wb_slave.vhd \
../../modules/timing/hpll_period_detect.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../modules/wr_tbi_phy/disparity_gen_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../modules/wr_pps_gen/pps_gen_wb.vhd \
../../modules/wr_endpoint/ep_rx_status_reg_insert.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd \
../../modules/wr_streamers/xtx_streamers_stats.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd \
../../modules/wr_endpoint/xwr_endpoint.vhd \
../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd \
../../modules/wr_streamers/streamers_priv_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../../modules/wr_endpoint/ep_registers_pkg.vhd \
../../modules/wr_endpoint/ep_autonegotiation.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../modules/wr_endpoint/ep_tx_packet_injection.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../modules/wr_endpoint/endpoint_private_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../modules/wr_endpoint/ep_clock_alignment_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd \
../../modules/wr_endpoint/ep_tx_crc_inserter.vhd \
../../modules/wr_eca/eca.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../board/common/wr_board_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../modules/wr_endpoint/ep_rx_early_address_match.vhd \
../../modules/wr_si57x_interface/wr_si57x_interface.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_funct_match.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../modules/wr_endpoint/wr_endpoint.vhd \
../../modules/wr_streamers/escape_detector.vhd \
../../modules/wr_softpll_ng/spll_period_detect.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../modules/wr_endpoint/ep_ts_counter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../modules/wr_eca/eca_ac_wbm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../modules/wr_eca/eca_data.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../modules/wr_eca/eca_queue.vhd \
../../modules/wr_mini_nic/minic_wbgen2_pkg.vhd \
../../modules/wr_eca/eca_auto_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../modules/fabric/xwrf_loopback/xwrf_loopback.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../modules/wr_endpoint/ep_rx_buffer.vhd \
../../modules/wr_mini_nic/minic_packet_buffer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../modules/wr_eca/eca_internals_pkg.vhd \
../../modules/wr_streamers/xtx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd \
../../modules/wr_dacs/cute_serial_dac_arb.vhd \
../../ip_cores/general-cores/modules/common/gc_comparator.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../modules/wr_mini_nic/wr_mini_nic.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_pass_fifo.vhd \
../../modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_commit_len_fifo.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd \
../../platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/vme64x-core/hdl/rtl/xvme64x_core.vhd \
../../ip_cores/etherbone-core/hdl/eb_master_core/eb_framer.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_register.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../modules/timing/pulse_gen.vhd \
../../modules/wr_endpoint/ep_rx_vlan_unit.vhd \
../../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../../board/cute/cute_reset_gen.vhd \
../../modules/wr_softpll_ng/wr_softpll_ng.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_ethernet_slave.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd \
../../modules/wr_endpoint/ep_1000basex_pcs.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd \
../../modules/wr_streamers/wr_streamers_wb.vhd \
../../modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_line.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../modules/wr_eca/eca_tag_channel.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../modules/wr_eca/eca_tdp.vhd \
../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../modules/wr_eca/eca_search.vhd \
../../modules/wr_eca/eca_queue_auto_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/vme64x-core/hdl/rtl/vme_cr_csr_space.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd \
../../modules/wr_eca/eca_queue_auto.vhd \
../../modules/wr_streamers/tx_streamer.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd \
../../modules/wr_eca/eca_wr_time.vhd \
../../modules/wr_streamers/xrx_streamer.vhd \
../../modules/wr_endpoint/ep_rx_bypass_queue.vhd \
../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../modules/wr_streamers/escape_inserter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_tag_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../modules/wr_endpoint/ep_leds_controller.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd \
../../modules/wr_eca/eca_walker.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../modules/wr_softpll_ng/softpll_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd \
../../modules/wr_endpoint/ep_packet_filter.vhd \
../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd
#target for running synthesis in the remote location
remote: __test_for_remote_synthesis_variables generate_tcl __send __do_synthesis
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -e 'ssh -p $(PORT)' -Ravl $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ifeq (x$(HDLMAKE_RSYNTH_USE_SCREEN), x1)
ssh -t $(USER)@$(SERVER) 'screen bash -c "cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl"'
else
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && $(HDLMAKE_RSYNTH_ISE_PATH)/xtclsh run.tcl'
endif
sync:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)/$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/cute_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "csg324"
syn_top = "cute_wr_ref_top"
syn_project = "cute_wr_ref.xise"
syn_tool = "ise"
modules = { "local" : "../../top/cute_ref_design/"}
syn/cute_ref_design/cute_wr_ref.xise 0 → 100644
View file @ f1b7521d
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgenplus/wbgenplus_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../modules/timing/oserdes_4_to_1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="390"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="384"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="388"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_readout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="389"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="390"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="391"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/matrix_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="392"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
top/cute_ref_design/Manifest.py 0 → 100644
View file @ f1b7521d
fetchto = "../../ip_cores"
files = [
"cute_wr_ref_top.vhd",
"cute_wr_ref_top.ucf",
]
modules = {
"local" : [
"../../",
"../../board/cute",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
}
top/cute_ref_design/cute_core_ref_top.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : WRPC reference design for CUTE
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : cute_core_ref_top.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : Tsinghua Univ. (DEP), CERN
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CUTE.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CUTE board.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-- CUTE: https://www.ohwr.org/projects/cute-wr-dp
--
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_cute_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity cute_core_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_sfp0_enable : integer:= 1;
g_sfp1_enable : integer:= 0;
g_cute_version : string:= "2.2";
g_aux_sdb : t_sdb_device := c_xwb_xil_multiboot_sdb;
g_multiboot_enable : boolean:= false
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk20m_vcxo_i : in std_logic; -- 20mhz vcxo clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
sfp0_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp0_ref_clk_n : in std_logic;
sfp1_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp1_ref_clk_n : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk : out std_logic;
plldac_din : out std_logic;
plldac_clr_n : out std_logic;
plldac_load_n : out std_logic;
plldac_sync_n : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp0_tx_p : out std_logic;
sfp0_tx_n : out std_logic;
sfp0_rx_p : in std_logic;
sfp0_rx_n : in std_logic;
sfp0_det : in std_logic; -- sfp detect
sfp0_scl_i : in std_logic; -- scl
sfp0_scl_o : out std_logic; -- scl
sfp0_sda_i : in std_logic; -- sda
sfp0_sda_o : out std_logic; -- sda
sfp0_tx_fault : in std_logic;
sfp0_tx_disable : out std_logic;
sfp0_los : in std_logic;
--sfp1_tx_p : out std_logic;
--sfp1_tx_n : out std_logic;
--sfp1_rx_p : in std_logic;
--sfp1_rx_n : in std_logic;
--sfp1_det : in std_logic; -- sfp detect
--sfp1_scl_i : in std_logic; -- scl
--sfp1_scl_o : out std_logic; -- scl
--sfp1_sda_i : in std_logic; -- sda
--sfp1_sda_o : out std_logic; -- sda
--sfp1_tx_fault : in std_logic;
--sfp1_tx_disable : out std_logic;
--sfp1_tx_los : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
onewire_oen_o : out std_logic;
onewire_i : in std_logic; -- 1-wire interface to ds18b20
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rx : in std_logic;
uart_tx : out std_logic;
---------------------------------------------------------------------------
-- I2C configuration EEPROM interface
---------------------------------------------------------------------------
eeprom_scl_i : in std_logic;
eeprom_scl_o : out std_logic;
eeprom_sda_i : in std_logic;
eeprom_sda_o : out std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
---------------------------------------------------------------------------
-- Miscellanous I/O pins
---------------------------------------------------------------------------
-- user interface
sfp0_led : out std_logic;
sfp1_led : out std_logic;
ext_clk : out std_logic;
usr_button : in std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
pps_out : out std_logic
);
end cute_core_ref_top;
architecture rtl of cute_core_ref_top is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal pps : std_logic;
signal pps_csync : std_logic;
attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps";
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_tai_valid : std_logic;
signal tm_tai_valid_d1 : std_logic;
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(0 downto 0);
-- Wishbone buse(s) to slaves attached to crossbar
signal cnx_slave_out : t_wishbone_slave_out_array(0 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(0 downto 0);
-- Not needed now, but useful if application cores are added
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
begin
u_wr_core : xwrc_board_cute
generic map(
g_dpram_initf => g_dpram_initf,
g_sfp0_enable => g_sfp0_enable,
g_sfp1_enable => g_sfp1_enable,
g_aux_sdb => g_aux_sdb,
g_cute_version => g_cute_version,
g_phy_refclk_sel => 4,
g_multiboot_enable => g_multiboot_enable)
port map (
areset_n_i => usr_button,
clk_20m_vcxo_i => clk20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp0_p_i => sfp0_ref_clk_p,
clk_125m_gtp0_n_i => sfp0_ref_clk_n,
clk_125m_gtp1_p_i => sfp1_ref_clk_p,
clk_125m_gtp1_n_i => sfp1_ref_clk_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_10m_ext_o => ext_clk,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => plldac_sclk,
plldac_din_o => plldac_din,
plldac_clr_n_o => plldac_clr_n,
plldac_load_n_o => plldac_load_n,
plldac_sync_n_o => plldac_sync_n,
sfp0_txp_o => sfp0_tx_p,
sfp0_txn_o => sfp0_tx_n,
sfp0_rxp_i => sfp0_rx_p,
sfp0_rxn_i => sfp0_rx_n,
sfp0_det_i => sfp0_det,
sfp0_scl_i => sfp0_scl_i,
sfp0_scl_o => sfp0_scl_o,
sfp0_sda_i => sfp0_sda_i,
sfp0_sda_o => sfp0_sda_o,
sfp0_rate_select_o => open,
sfp0_tx_fault_i => sfp0_tx_fault,
sfp0_tx_disable_o => sfp0_tx_disable,
sfp0_los_i => sfp0_los,
--sfp1_txp_o => sfp1_tx_p,
--sfp1_txn_o => sfp1_tx_n,
--sfp1_rxp_i => sfp1_rx_p,
--sfp1_rxn_i => sfp1_rx_n,
--sfp1_det_i => sfp1_det,
--sfp1_scl_i => sfp1_scl_i,
--sfp1_scl_o => sfp1_scl_o,
--sfp1_sda_i => sfp1_sda_i,
--sfp1_sda_o => sfp1_sda_o,
--sfp1_rate_select_o => open,
--sfp1_tx_fault_i => sfp1_tx_fault,
--sfp1_tx_disable_o => sfp1_tx_disable,
--sfp1_los_i => sfp1_tx_los,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rx,
uart_txd_o => uart_tx,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_slave_out(0),
wb_slave_i => cnx_slave_in(0),
wb_eth_master_o => cnx_master_out(0),
wb_eth_master_i => cnx_master_in(0),
tm_link_up_o => open,
tm_time_valid_o => tm_tai_valid,
tm_tai_o => tm_tai,
tm_cycles_o => open,
led_act_o => sfp0_led,
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_csync_o => pps_csync,
link_ok_o => usr_led2);
cnx_slave_in <= cnx_master_out;
cnx_master_in <= cnx_slave_out;
end rtl;
top/cute_ref_design/cute_wr_ref_top.ucf 0 → 100644
View file @ f1b7521d
config vccaux = 3.3;
# bank 0
#net "clk1_m2c_p" loc = b3;net "clk1_m2c_p" iostandard = lvds_33;
#net "clk1_m2c_n" loc = a3;net "clk1_m2c_n" iostandard = lvds_33;
#net "la03_p" loc = e6;net "la03_p" iostandard = lvds_33;
#net "la03_n" loc = f7;net "la03_n" iostandard = lvds_33;
#net "la01_cc_p" loc = g8;net "la01_cc_p" iostandard = lvds_33;
#net "la01_cc_n" loc = e8;net "la01_cc_n" iostandard = lvds_33;
#net "la20_p" loc = g9;net "la20_p" iostandard = lvds_33;
#net "la20_n" loc = g11;net "la20_n" iostandard = lvds_33;
#net "la30_p" loc = c15;net "la30_p" iostandard = lvds_33;
#net "la30_n" loc = a15;net "la30_n" iostandard = lvds_33;
#net "la29_p" loc = b16;net "la29_p" iostandard = lvds_33;
#net "la29_n" loc = a16;net "la29_n" iostandard = lvds_33;
#net "la24_p" loc = e14;net "la24_p" iostandard = lvds_33;
#net "la24_n" loc = d15;net "la24_n" iostandard = lvds_33;
net "clk_125m_pllref_p_i" loc = f12;
net "clk_125m_pllref_p_i" iostandard = lvds_33;
net "clk_125m_pllref_n_i" loc = e12;
net "clk_125m_pllref_n_i" iostandard = lvds_33;
# bank 1
net "pps_out" loc = c18;net "pps_out" iostandard = lvcmos33;
net "usr_led1" loc = e18;net "usr_led1" iostandard = lvcmos33;
net "usr_led2" loc = d17;net "usr_led2" iostandard = lvcmos33;
#net "sfp1_tx_los" loc = f18;net "sfp1_tx_los" iostandard = lvcmos33;
#net "sfp1_tx_fault" loc = h16;net "sfp1_tx_fault" iostandard = lvcmos33;
#net "sfp1_det" loc = g16;net "sfp1_det" iostandard = lvcmos33;
#net "sfp1_scl" loc = g18;net "sfp1_scl" iostandard = lvcmos33;
#net "sfp1_sda" loc = h17;net "sfp1_sda" iostandard = lvcmos33;
#net "sfp1_tx_disable" loc = h18;net "sfp1_tx_disable" iostandard = lvcmos33;
net "eeprom_sda" loc = j18;net "eeprom_sda" iostandard = lvcmos33;
net "eeprom_scl" loc = k17;net "eeprom_scl" iostandard = lvcmos33;
#net "la32_p" loc = p17;net "la32_p" iostandard = lvds_33;
#net "la32_n" loc = p18;net "la32_n" iostandard = lvds_33;
#net "la33_p" loc = t17;net "la33_p" iostandard = lvds_33;
#net "la33_n" loc = t18;net "la33_n" iostandard = lvds_33;
#net "la31_p" loc = u17;net "la31_p" iostandard = lvds_33;
#net "la31_n" loc = u18;net "la31_n" iostandard = lvds_33;
# bank 2
net "flash_sclk_o" loc = r15;net "flash_sclk_o" iostandard = lvcmos33;
net "flash_ncs_o" loc = v3;net "flash_ncs_o" iostandard = lvcmos33;
net "flash_mosi_o" loc = t13;net "flash_mosi_o" iostandard = lvcmos33;
net "flash_miso_i" loc = r13;net "flash_miso_i" iostandard = lvcmos33;
#net "la28_p" loc = u16;net "la28_p" iostandard = lvds_33;
#net "la28_n" loc = v16;net "la28_n" iostandard = lvds_33;
#net "la25_p" loc = u15;net "la25_p" iostandard = lvds_33;
#net "la25_n" loc = v15;net "la25_n" iostandard = lvds_33;
#net "la26_p" loc = t14;net "la26_p" iostandard = lvds_33;
#net "la26_n" loc = v14;net "la26_n" iostandard = lvds_33;
#net "la21_p" loc = u13;net "la21_p" iostandard = lvds_33;
#net "la21_n" loc = v13;net "la21_n" iostandard = lvds_33;
#net "la27_p" loc = m11;net "la27_p" iostandard = lvds_33;
#net "la27_n" loc = n11;net "la27_n" iostandard = lvds_33;
#net "la18_cc_p" loc = r11;net "la18_cc_p" iostandard = lvds_33;
#net "la18_cc_n" loc = t11;net "la18_cc_n" iostandard = lvds_33;
#net "la22_p" loc = t12;net "la22_p" iostandard = lvds_33;
#net "la22_n" loc = v12;net "la22_n" iostandard = lvds_33;
#net "la23_p" loc = n10;net "la23_p" iostandard = lvds_33;
#net "la23_n" loc = p11;net "la23_n" iostandard = lvds_33;
#net "la14_p" loc = m10;net "la14_p" iostandard = lvds_33;
#net "la14_n" loc = n9;net "la14_n" iostandard = lvds_33;
#net "la15_p" loc = u11;net "la15_p" iostandard = lvds_33;
#net "la15_n" loc = v11;net "la15_n" iostandard = lvds_33;
#net "la19_p" loc = r10;net "la19_p" iostandard = lvds_33;
#net "la19_n" loc = t10;net "la19_n" iostandard = lvds_33;
#net "la07_p" loc = u10;net "la07_p" iostandard = lvds_33;
#net "la07_n" loc = v10;net "la07_n" iostandard = lvds_33;
#net "la16_p" loc = r8;net "la16_p" iostandard = lvds_33;
#net "la16_n" loc = t8;net "la16_n" iostandard = lvds_33;
#net "la13_p" loc = t9;net "la13_p" iostandard = lvds_33;
#net "la13_n" loc = v9;net "la13_n" iostandard = lvds_33;
#net "la17_cc_p" loc = m8;net "la17_cc_p" iostandard = lvds_33;
#net "la17_cc_n" loc = n8;net "la17_cc_n" iostandard = lvds_33;
#net "la04_p" loc = t8;net "la04_p" iostandard = lvds_33;
#net "la04_n" loc = v8;net "la04_n" iostandard = lvds_33;
#net "la02_p" loc = u7;net "la02_p" iostandard = lvds_33;
#net "la02_n" loc = v7;net "la02_n" iostandard = lvds_33;
#net "la00_cc_p" loc = n7;net "la00_cc_p" iostandard = lvds_33;
#net "la00_cc_n" loc = p8;net "la00_cc_n" iostandard = lvds_33;
#net "la09_p" loc = t6;net "la09_p" iostandard = lvds_33;
#net "la09_n" loc = v6;net "la09_n" iostandard = lvds_33;
#net "la11_p" loc = r7;net "la11_p" iostandard = lvds_33;
#net "la11_n" loc = t7;net "la11_n" iostandard = lvds_33;
#net "la12_p" loc = n6;net "la12_p" iostandard = lvds_33;
#net "la12_n" loc = p7;net "la12_n" iostandard = lvds_33;
#net "la10_p" loc = r5;net "la10_p" iostandard = lvds_33;
#net "la10_n" loc = t5;net "la10_n" iostandard = lvds_33;
#net "clk0_m2c_p" loc = u5;net "clk0_m2c_p" iostandard = lvds_33;
#net "clk0_m2c_n" loc = v5;net "clk0_m2c_n" iostandard = lvds_33;
#net "la08_p" loc = r3;net "la08_p" iostandard = lvds_33;
#net "la08_n" loc = t3;net "la08_n" iostandard = lvds_33;
#net "la06_p" loc = t4;net "la06_p" iostandard = lvds_33;
#net "la06_n" loc = v4;net "la06_n" iostandard = lvds_33;
#net "la05_p" loc = n5;net "la05_p" iostandard = lvds_33;
#net "la05_n" loc = p6;net "la05_n" iostandard = lvds_33;
# bank 3
net "clk20m_vcxo_i" loc = h1;net "clk20m_vcxo_i" iostandard = lvcmos33;
net "usr_button" loc = h3;net "usr_button" iostandard = lvcmos33;
net "one_wire" loc = h2;net "one_wire" iostandard = lvcmos33;
net "uart_rx" loc = j1;net "uart_rx" iostandard = lvcmos33;
net "uart_tx" loc = j3;net "uart_tx" iostandard = lvcmos33;
net "plldac_din" loc = c1;net "plldac_din" iostandard = lvcmos33;
net "plldac_clr_n" loc = e1;net "plldac_clr_n" iostandard = lvcmos33;
net "plldac_sclk" loc = c2;net "plldac_sclk" iostandard = lvcmos33;
net "plldac_sync_n" loc = d1;net "plldac_sync_n" iostandard = lvcmos33;
net "plldac_load_n" loc = d2;net "plldac_load_n" iostandard = lvcmos33;
net "sfp1_led" loc = g3;net "sfp1_led" iostandard = lvcmos33;
net "sfp0_led" loc = k4;net "sfp0_led" iostandard = lvcmos33;
net "sfp0_los" loc = g1;net "sfp0_los" iostandard = lvcmos33;
net "sfp0_det" loc = f3;net "sfp0_det" iostandard = lvcmos33;
net "sfp0_scl" loc = f1;net "sfp0_scl" iostandard = lvcmos33;
net "sfp0_sda" loc = e4;net "sfp0_sda" iostandard = lvcmos33;
net "sfp0_tx_fault" loc = d3;net "sfp0_tx_fault" iostandard = lvcmos33;
net "sfp0_tx_disable" loc = e3;net "sfp0_tx_disable" iostandard = lvcmos33;
# bank gtp
net "sfp0_ref_clk_n" loc = c9;net "sfp0_ref_clk_n" iostandard = lvcmos33;
net "sfp0_ref_clk_p" loc = d9;net "sfp0_ref_clk_p" iostandard = lvcmos33;
net "sfp0_rx_n" loc = c7;
net "sfp0_rx_p" loc = d7;
net "sfp0_tx_n" loc = a6;
net "sfp0_tx_p" loc = b6;
#net "sfp1_ref_clk_n" loc = e10;net "sfp1_ref_clk_n" iostandard = lvcmos33;
#net "sfp1_ref_clk_p" loc = f10;net "sfp1_ref_clk_p" iostandard = lvcmos33;
#net "sfp1_rx_n" loc = c13;
#net "sfp1_rx_p" loc = d13;
#net "sfp1_tx_n" loc = a14;
#net "sfp1_tx_p" loc = b14;
#net "mgtrx0_n" loc = c5;
#net "mgtrx0_p" loc = d5;
#net "mgttx0_n" loc = a4;
#net "mgttx0_p" loc = b4;
#---------------------------------------------------------------------------------------------
# clock period information
#---------------------------------------------------------------------------------------------
NET "clk20m_vcxo_i" TNM_NET = clk20m_vcxo_i;
TIMESPEC TS_clk20m_vcxo_i = PERIOD "clk20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "sfp0_ref_clk_p" TNM_NET = sfp0_ref_clk_p;
TIMESPEC TS_sfp0_ref_clk_p = PERIOD "sfp0_ref_clk_p" 8 ns HIGH 50%;
NET "sfp0_ref_clk_n" TNM_NET = sfp0_ref_clk_n;
TIMESPEC TS_sfp0_ref_clk_n = PERIOD "sfp0_ref_clk_n" 8 ns HIGH 50%;
NET "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" TNM_NET = u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>;
TIMESPEC TS_u_wr_core_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch_gtp_clkout_int_1_ = PERIOD "u_wr_core/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch*_gtp_clkout_int<1>" 8 ns HIGH 50%;
inst "pps_out" iob = force;
net "pps_out" drive = 24 | slew = fast;
#cute-wr-dp V2.1
#net "ext_clk" loc = f2;net "ext_clk" iostandard = lvcmos33;
#cute-wr-dp V2.2
net "ext_clk" loc = k3;net "ext_clk" iostandard = lvcmos33;
net "ext_clk" drive = 24 | slew = fast;
top/cute_ref_design/cute_wr_ref_top.vhd 0 → 100644
View file @ f1b7521d
-------------------------------------------------------------------------------
-- Title : WRPC reference design for CUTE
-- Project : WR PTP Core
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-------------------------------------------------------------------------------
-- File : cute_wr_ref_top.vhd
-- Author(s) : Hongming Li <lihm.thu@foxmail.com>
-- Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : Tsinghua Univ. (DEP), CERN
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the CUTE.
--
-- This is a reference top HDL that instanciates the WR PTP Core together with
-- its peripherals to be run on a CUTE board.
--
-- There are two main usecases for this HDL file:
-- * let new users easily synthesize a WR PTP Core bitstream that can be run on
-- reference hardware
-- * provide a reference top HDL file showing how the WRPC can be instantiated
-- in HDL projects.
--
-- CUTE: https://www.ohwr.org/projects/cute-wr-dp
--
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.wr_board_pkg.all;
use work.wr_cute_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity cute_wr_ref_top is
generic (
g_dpram_initf : string := "../../bin/wrpc/wrc_phy8.bram";
g_sfp0_enable : integer:= 1;
g_sfp1_enable : integer:= 0;
g_cute_version : string:= "2.2";
g_aux_sdb : t_sdb_device := c_xwb_xil_multiboot_sdb;
g_multiboot_enable : boolean:= false
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk20m_vcxo_i : in std_logic; -- 20mhz vcxo clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
sfp0_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp0_ref_clk_n : in std_logic;
sfp1_ref_clk_p : in std_logic; -- dedicated clock for xilinx gtp transceiver
sfp1_ref_clk_n : in std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk : out std_logic;
plldac_din : out std_logic;
plldac_clr_n : out std_logic;
plldac_load_n : out std_logic;
plldac_sync_n : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp0_tx_p : out std_logic;
sfp0_tx_n : out std_logic;
sfp0_rx_p : in std_logic;
sfp0_rx_n : in std_logic;
sfp0_det : in std_logic; -- sfp detect
sfp0_scl : inout std_logic; -- scl
sfp0_sda : inout std_logic; -- sda
sfp0_tx_fault : in std_logic;
sfp0_tx_disable : out std_logic;
sfp0_los : in std_logic;
--sfp1_tx_p : out std_logic;
--sfp1_tx_n : out std_logic;
--sfp1_rx_p : in std_logic;
--sfp1_rx_n : in std_logic;
--sfp1_det : in std_logic; -- sfp detect
--sfp1_scl : inout std_logic; -- scl
--sfp1_sda : inout std_logic; -- sda
--sfp1_tx_fault : in std_logic;
--sfp1_tx_disable : out std_logic;
--sfp1_tx_los : in std_logic;
---------------------------------------------------------------------------
-- Onewire interface
---------------------------------------------------------------------------
one_wire : inout std_logic; -- 1-wire interface to ds18b20
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rx : in std_logic;
uart_tx : out std_logic;
---------------------------------------------------------------------------
-- I2C configuration EEPROM interface
---------------------------------------------------------------------------
eeprom_scl : inout std_logic;
eeprom_sda : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
flash_sclk_o : out std_logic;
flash_ncs_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic:='1';
---------------------------------------------------------------------------
-- Miscellanous I/O pins
---------------------------------------------------------------------------
-- user interface
sfp0_led : out std_logic;
sfp1_led : out std_logic;
ext_clk : out std_logic;
usr_button : in std_logic;
usr_led1 : out std_logic;
usr_led2 : out std_logic;
pps_out : out std_logic
);
end cute_wr_ref_top;
architecture rtl of cute_wr_ref_top is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- I2C EEPROM
signal eeprom_scl_o : std_logic;
signal eeprom_scl_i : std_logic;
signal eeprom_sda_o : std_logic;
signal eeprom_sda_i : std_logic;
-- OneWire
signal onewire_i : std_logic;
signal onewire_oen_o : std_logic;
-- SFP
signal sfp0_scl_i : std_logic;
signal sfp0_scl_o : std_logic;
signal sfp0_sda_i : std_logic;
signal sfp0_sda_o : std_logic;
signal sfp1_scl_i : std_logic;
signal sfp1_scl_o : std_logic;
signal sfp1_sda_i : std_logic;
signal sfp1_sda_o : std_logic;
signal pps : std_logic;
signal pps_csync : std_logic;
attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps";
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_time_valid : std_logic;
signal tm_link_up : std_logic;
signal pps_led : std_logic;
signal led_act : std_logic;
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(0 downto 0);
-- Wishbone buse(s) to slaves attached to crossbar
signal cnx_slave_out : t_wishbone_slave_out_array(0 downto 0);
signal cnx_slave_in : t_wishbone_slave_in_array(0 downto 0);
-- Not needed now, but useful if application cores are added
signal clk_sys_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
begin
u_wr_core : xwrc_board_cute
generic map(
g_dpram_initf => g_dpram_initf,
g_sfp0_enable => g_sfp0_enable,
g_sfp1_enable => g_sfp1_enable,
g_aux_sdb => g_aux_sdb,
g_cute_version => g_cute_version,
g_phy_refclk_sel => 4,
g_multiboot_enable => g_multiboot_enable)
port map (
areset_n_i => usr_button,
clk_20m_vcxo_i => clk20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp0_p_i => sfp0_ref_clk_p,
clk_125m_gtp0_n_i => sfp0_ref_clk_n,
clk_125m_gtp1_p_i => sfp1_ref_clk_p,
clk_125m_gtp1_n_i => sfp1_ref_clk_n,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_10m_ext_o => ext_clk,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
plldac_sclk_o => plldac_sclk,
plldac_din_o => plldac_din,
plldac_clr_n_o => plldac_clr_n,
plldac_load_n_o => plldac_load_n,
plldac_sync_n_o => plldac_sync_n,
sfp0_txp_o => sfp0_tx_p,
sfp0_txn_o => sfp0_tx_n,
sfp0_rxp_i => sfp0_rx_p,
sfp0_rxn_i => sfp0_rx_n,
sfp0_det_i => sfp0_det,
sfp0_scl_i => sfp0_scl_i,
sfp0_scl_o => sfp0_scl_o,
sfp0_sda_i => sfp0_sda_i,
sfp0_sda_o => sfp0_sda_o,
sfp0_rate_select_o => open,
sfp0_tx_fault_i => sfp0_tx_fault,
sfp0_tx_disable_o => sfp0_tx_disable,
sfp0_los_i => sfp0_los,
--sfp1_txp_o => sfp1_tx_p,
--sfp1_txn_o => sfp1_tx_n,
--sfp1_rxp_i => sfp1_rx_p,
--sfp1_rxn_i => sfp1_rx_n,
--sfp1_det_i => sfp1_det,
--sfp1_scl_i => sfp1_scl_i,
--sfp1_scl_o => sfp1_scl_o,
--sfp1_sda_i => sfp1_sda_i,
--sfp1_sda_o => sfp1_sda_o,
--sfp1_rate_select_o => open,
--sfp1_tx_fault_i => sfp1_tx_fault,
--sfp1_tx_disable_o => sfp1_tx_disable,
--sfp1_los_i => sfp1_tx_los,
eeprom_scl_i => eeprom_scl_i,
eeprom_scl_o => eeprom_scl_o,
eeprom_sda_i => eeprom_sda_i,
eeprom_sda_o => eeprom_sda_o,
onewire_i => onewire_i,
onewire_oen_o => onewire_oen_o,
uart_rxd_i => uart_rx,
uart_txd_o => uart_tx,
flash_sclk_o => flash_sclk_o,
flash_ncs_o => flash_ncs_o,
flash_mosi_o => flash_mosi_o,
flash_miso_i => flash_miso_i,
wb_slave_o => cnx_slave_out(0),
wb_slave_i => cnx_slave_in(0),
wb_eth_master_o => cnx_master_out(0),
wb_eth_master_i => cnx_master_in(0),
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
tm_tai_o => tm_tai,
tm_cycles_o => open,
led_act_o => led_act,
led_link_o => open,
pps_p_o => pps_out,
pps_led_o => pps_led,
pps_csync_o => pps_csync,
link_ok_o => open);
cnx_slave_in <= cnx_master_out;
cnx_master_in <= cnx_slave_out;
-- Tristates for configuration EEPROM
eeprom_scl <= '0' when eeprom_scl_o = '0' else 'Z';
eeprom_sda <= '0' when eeprom_sda_o = '0' else 'Z';
eeprom_scl_i <= eeprom_scl;
eeprom_sda_i <= eeprom_sda;
-- Tristates for SFP EEPROM
sfp0_scl <= '0' when sfp0_scl_o = '0' else 'Z';
sfp0_sda <= '0' when sfp0_sda_o = '0' else 'Z';
sfp0_scl_i <= sfp0_scl;
sfp0_sda_i <= sfp0_sda;
--sfp1_scl <= '0' when sfp1_scl_o = '0' else 'Z';
--sfp1_sda <= '0' when sfp1_sda_o = '0' else 'Z';
--sfp1_scl_i <= sfp1_scl;
--sfp1_sda_i <= sfp1_sda;
-- Tristates for Onewire
one_wire <= '0' when onewire_oen_o = '1' else 'Z';
onewire_i <= one_wire;
sfp0_led <= not led_act;
sfp1_led <= not pps_led;
usr_led1 <= not tm_time_valid;
usr_led2 <= not tm_link_up;
end rtl;
top/readme_platforms.txt
View file @ f1b7521d
......@@ -2,4 +2,5 @@ Available device plaftorms (so far):
------------------------------------
gsi_scu - GSI's Scalable Control Unit (SCU), based on Altera ArriaII-GX (EP2AGX125)
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
\ No newline at end of file
spec_1_1 - CERN's Simple PCI-Express Carrier (SPEC), based on Xilinx Spartan-6 (XC6SLX45). Version 1.1 or newer (pin-compatible)
cute - TSINGHUA's CUTEDP, based on Xilinx Spartan-6 (XC6SLX45T).
\ No newline at end of file
top/spec_1_1/wr_streamers_demo/spec_top.vhd
View file @ f1b7521d
......@@ -632,7 +632,8 @@ begin
g_enable_ch1 => 1,
g_simulation => g_simulation)
port map (
gtp_clk_i => clk_gtp,
gtp0_clk_i => '0',
gtp1_clk_i => clk_gtp,
ch1_ref_clk_i => clk_ref,
......
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