-
Dimitris Lampridis authored
GTP reference clock is connected to CLK01 and/or CLK11 in our instance of GTP_DUAL. According to UG386, figure 2-3, page 41, REFSELDYPLLx must be set to '4' to select CLK10/CLK11. This is done in order to ensure backward compatibility with previous versions of the Xilinx platform support package.
99932d24
Name |
Last commit
|
Last update |
---|---|---|
bin | ||
board | ||
ip_cores | ||
modules | ||
platform | ||
sim | ||
syn | ||
testbench | ||
top | ||
.gitignore | ||
.gitmodules | ||
Manifest.py |