WR2RF-VME
Project description
This is a VME card that may be used to receive and recover the RF signal, bunch and revolution clocks over a White Rabbit network. Primarily, this card will function as a diagnostic card for the BE-RF group. It will also be required to regenerate the bunch and turn clocks to drive the BST-Master and the existing TTC system.
Whilst this board is targeting a specific application at CERN, this design could be used to recover RF signals transmitted through an Ethernet network. The card is designed to support a large range of frequency generation via some mounting options.
The RF signal will be sourced directly from the Low Level RF system through the transmission of Frequency Tuning Words (FTW). The LLRF utilises a DDS to generate the required RF, enabling the FTWs to be extracted and directly encoded into packets and then broadcast on a White Rabbit network.
This VME card receives packets that contain FTWs and IQ setpoints from the LLRF system. Then, using a FPGA with an assortment of analog components, this design is able to recover the original RF signal.
Main Features
This VME card can recover two RF channels, each comprising:
- RF signal (up to ~400 MHz (see Nyquist limitations of the AD9912 1 GHz DDS).
- Bunch or event Clock.
- Turn or event Clock.
Contains monitoring options for the White Rabbit clocks:
- 10 MHz in/out SMA.
- PPS in/out SMA.
- White Rabbit clock.
General purpose LEMO connections:
- 4x GPIO LEMO.
- External clock input.
- External stop/sync input for Trigger Unit usage.
Dual SFP connectors with White Rabbit compliant interfaces.
FPGA, Connectivity and IO
- Xilinx Kintex-7 FPGA XC7K160T-2FBG676C
- Dual SFP connectors that are White Rabbit compliant.
- External high performance 100 MHz OCXO oscillator, for White Rabbit 10 MHz clock clean-up.
- External PLL, producing clean 125 MHz, 250 MHz and 1 GHz clocks.
- DDS chip capable of producing a local oscillator frequency at 223.5 MHz.
- Front panel LEMO: 4x Timing in/outs (TTL, 50 Ω).
- Front panel LEMO: External start, input (TTL, 50 Ω).
- Front panel LEMO: External clock, input (TTL, 50 Ω).
- Front panel SMA: White Rabbit clock output.
- Front panel SMA/SMC: 10 MHz out/in reference clock from/to 10 MHz clock cleaning PLL.
- Dual channel recovery of two RF clocks, specifically to support slip-stacking at two different frequencies.
- Each RF channel requires:
- DAC, LPF and Mixer pipeline. The LO frequency is sourced from the DDS at 223.5 MHz for both channels.
- Front panel SMA: RF Out (0 dBm, 50 Ω).
- Front panel SMA: Trigger 1 (1 V, 50 ns, 50 Ω). Supporting a bunch clock output.
- Front panel SMA: Trigger 2 (1 V, 50 ns, 50 Ω). Supporting an orbit/revolution clock output.
Project information
- Gateware release
- Hardware release and production documentation: EDA-04287
- Specifications on EDMS
- VME P0 Connector Allocations
- Greg Hagmann's initial functional block diagram illustrating the main IO features of thevcard.
- HW trigger questions for previous designers
- V1.0 Schematic Review
Contacts
General question about project
- Dimitris Lampridis - CERN
- John Gill - CERN
Commercial producers
- This board is not commercially available.
Status
Date | Event |
---|---|
01-10-2018 | First technical discussions about the specification. |
26-10-2018 | Following a meeting with: Javier Serrano, Greg Hagmann, Arthur Spierer, Tom Levens, Manuel González Berges and John Gill; it was agreed for CO to develop this module based on GH's design. |
05-11-2019 | Specifications published on EDMS. |
01-12-2019 | Schematic work started. |
20-01-2020 | RF channel analog datapath complete. |
04-02-2020 | FPGA pin-planning, draft complete. |
20-04-2020 | First draft of schematics complete. |
15-06-2020 | End of v1 schematic review. |
14-07-2020 | Release of v1 schematics. |
02-09-2020 | Plan to have five prototypes assembled by mid-November. |
20-10-2020 | PCB design reviewed, corrections to be made by the design office. |
26-10-2020 | PCB design ready. Production of V1 prototypes can start. |
08-12-2020 | Board bring-up commences. Prototypes delivered. |
22-01-2021 | Gateware v0.1.0 beta released, Card 0004 delivered to RF |
12-02-2021 | First installation. Card 3 installed in BA3 cfv-ba3-allbc2 slot3 + slot4 |
15-02-2021 | V2 PCB layout ready. |
26-02-2021 | Observing stable RF in both RF channels and trigger units relative to nco_reset. |
15-04-2021 | Capture of beam from PS in SPS using signals generated by WR2RF. |
13-09-2021 | Gateware/firmware release v0.14 incorporating updated RFNCO ip. |
05-11-2021 | Gateware/firmware release v0.15 and added PCB picture. |
06-04-2023 | Gateware release v0.16. |
25-05-2023 | Gateware release v0.17. |