- 26 Jan, 2017 3 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 25 Jan, 2017 3 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Previous commit contained serious error, as accidentally modified blo-input nets. It is corrected now + right nets assigned for PCB versioning
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- 24 Jan, 2017 4 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Testbench for burst mode testing updated. The overall gateware testbench also updated to show burst mode operation for short pulses
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- 16 Jan, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 13 Jan, 2017 1 commit
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Denia Bouhired-Ferrag authored
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- 21 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 20 Dec, 2016 2 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 16 Dec, 2016 4 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
Added tcl script used in release 3 of the gateware. Should work for future releases, but care must be taken to modify the file list
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Denia Bouhired-Ferrag authored
Adds updated project with settings from tcl scrip also added. Top module modified to have correct LED output
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- 13 Dec, 2016 1 commit
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Denia Bouhired-Ferrag authored
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- 07 Dec, 2016 2 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 10 Nov, 2016 2 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 06 Sep, 2016 2 commits
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Denia Bouhired-Ferrag authored
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Denia Bouhired-Ferrag authored
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- 27 Jan, 2015 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 26 Jan, 2015 1 commit
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Theodor-Adrian Stana authored
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- 23 Jan, 2015 1 commit
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Theodor-Adrian Stana authored
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- 10 Dec, 2014 1 commit
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Theodor-Adrian Stana authored
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- 30 Sep, 2014 1 commit
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Theodor-Adrian Stana authored
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- 29 Sep, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 26 Sep, 2014 3 commits
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Theodor-Adrian Stana authored
The following sections were updated: - 3.1 TTL input logic -- added reflection of no signal detect state in LSR - 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw - 3.3 Line input logic -- added reflection of no signal detect state in LSR - 3.4 Switches -- made figure more compact
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Theodor-Adrian Stana authored
Also updated ISE project file to test that nothing went wrong when these modules were deleted.
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Theodor-Adrian Stana authored
The issue with the first pulse inhibit mechanism was (again) that it needs to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled, otherwise the no signal detect block has no effect on the conv-common-gw block, due to sub-modules still being in a reset state. A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing the pulse signals to the conv-common-gw block. In addition to this modification, the FRONTFS and FRONTINVFS bits were added to the LSR inside conv-common-gw. The necessary additions were made here to account for the changes in the conv-common-gw interface.
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- 25 Sep, 2014 3 commits
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Theodor-Adrian Stana authored
Also prepared the ISE project file for v3.0 release
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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