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Conv TTL Blocking
Commit 00387791 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Add firmware support for TTL pulse repetition test (test01). 

Apart from this, a watchdog counter has been integrated into the
i2c_slave VHDL module; it resets the slave FSM after one second
if the master does not cycle the SCL line.
parent 8ab2fb99
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Showing with 2665 additions and 361 deletions
hdl/pts/rtl/Manifest.py
View file @ 00387791
files = [ files = [
"pts_regs.vhd", "pts_regs.vhd",
"pulse_cnt_wb.vhd",
"incr_counter.vhd", "incr_counter.vhd",
"clk_info_wb_slave.vhd" "clk_info_wb_slave.vhd"
] ]
hdl/pts/rtl/pulse_cnt_wb.vhd 0 → 100644
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This diff is collapsed.
hdl/pts/rtl/pulse_cnt_wb.wb 0 → 100644
View file @ 00387791
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_wb";
prefix = "pulse_cnt";
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 output";
prefix = "ch7o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH7 input";
prefix = "ch7i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 output";
prefix = "ch8o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH8 input";
prefix = "ch8i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 output";
prefix = "ch9o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH9 input";
prefix = "ch9i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 output";
prefix = "ch10o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH10 input";
prefix = "ch10i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/pts/syn/Makefile
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hdl/pts/syn/conv_ttl_blo_v2.gise
View file @ 00387791
...@@ -72,35 +72,35 @@ ...@@ -72,35 +72,35 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030704" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387848" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030730" xil_pn:in_ck="-952039140557355708" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366030704"> <transform xil_pn:end_ts="1366387909" xil_pn:in_ck="7459507639272444710" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366387848">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -118,11 +118,11 @@ ...@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030730" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366030730"> <transform xil_pn:end_ts="1366387909" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366387909">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030741" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366030730"> <transform xil_pn:end_ts="1366387921" xil_pn:in_ck="618428940982703508" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366387909">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
...@@ -131,8 +131,9 @@ ...@@ -131,8 +131,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030831" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366030741"> <transform xil_pn:end_ts="1366388222" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366387921">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/> <outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
...@@ -144,7 +145,7 @@ ...@@ -144,7 +145,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030895" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366030831"> <transform xil_pn:end_ts="1366388300" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366388222">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
...@@ -158,8 +159,9 @@ ...@@ -158,8 +159,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030923" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366030895"> <transform xil_pn:end_ts="1366388336" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366388300">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/> <outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
...@@ -169,7 +171,7 @@ ...@@ -169,7 +171,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1366030895" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366030883"> <transform xil_pn:end_ts="1366388300" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366388284">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/pts/syn/conv_ttl_blo_v2.ppr 0 → 100644
View file @ 00387791
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="28865206089a485a9c21d5aab1aa6830"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="All"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/pts/syn/conv_ttl_blo_v2.xise
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This diff is collapsed.
hdl/pts/top/Manifest.py
View file @ 00387791
...@@ -7,9 +7,13 @@ modules = { ...@@ -7,9 +7,13 @@ modules = {
"local" : [ "local" : [
"../../../../ip_cores/general-cores", "../../../../ip_cores/general-cores",
"../../reset_gen", "../../reset_gen",
"../../pulse_generator",
"../../rtm_detector", "../../rtm_detector",
"../../bicolor_led_ctrl", "../../bicolor_led_ctrl",
"../../vme64x_i2c", "../../vme64x_i2c",
"../rtl" "../rtl"
] ],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
} }
fetchto = "../../../../ip_cores"
hdl/pts/top/conv_ttl_blo_v2.ucf
View file @ 00387791
This diff is collapsed.
hdl/pts/top/conv_ttl_blo_v2.vhd
View file @ 00387791
This diff is collapsed.
hdl/pulse_generator/rtl/pulse_generator.vhd
View file @ 00387791
...@@ -79,6 +79,9 @@ entity pulse_generator is ...@@ -79,6 +79,9 @@ entity pulse_generator is
-- '0' - TYPE 2 (glitch-insensitive, with output jitter) -- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic; pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater -- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays. -- than internal gate delays.
trig_i : in std_logic; trig_i : in std_logic;
...@@ -180,7 +183,9 @@ begin ...@@ -180,7 +183,9 @@ begin
if (pulse_rst = '1') then if (pulse_rst = '1') then
pulse_type1 <= '0'; pulse_type1 <= '0';
elsif rising_edge(trig_i) then elsif rising_edge(trig_i) then
pulse_type1 <= '1'; if (enable_i = '1') then
pulse_type1 <= '1';
end if;
end if; end if;
end process p_pulse_type1; end process p_pulse_type1;
...@@ -192,7 +197,7 @@ begin ...@@ -192,7 +197,7 @@ begin
pulse_type1_d0 <= '0'; pulse_type1_d0 <= '0';
pulse_type1_d1 <= '0'; pulse_type1_d1 <= '0';
pulse_type1_d2 <= '0'; pulse_type1_d2 <= '0';
else elsif (enable_i = '1') then
pulse_type1_d0 <= pulse_type1; pulse_type1_d0 <= pulse_type1;
pulse_type1_d1 <= pulse_type1_d0; pulse_type1_d1 <= pulse_type1_d0;
pulse_type1_d2 <= pulse_type1_d1; pulse_type1_d2 <= pulse_type1_d1;
...@@ -206,10 +211,11 @@ begin ...@@ -206,10 +211,11 @@ begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if (rst_n_i = '0') then if (rst_n_i = '0') then
pulse_type2 <= '0'; pulse_type2 <= '0';
elsif (state = ST_PULSE_TYPE2) then elsif (enable_i = '1') then
pulse_type2 <= '1';
else
pulse_type2 <= '0'; pulse_type2 <= '0';
if (state = ST_PULSE_TYPE2) then
pulse_type2 <= '1';
end if;
end if; end if;
end if; end if;
end process p_pulse_type2; end process p_pulse_type2;
...@@ -241,7 +247,7 @@ begin ...@@ -241,7 +247,7 @@ begin
pulse_rst <= '1'; pulse_rst <= '1';
width_cnt <= (others => '0'); width_cnt <= (others => '0');
trig_degl_d0 <= '0'; trig_degl_d0 <= '0';
else elsif (enable_i = '1') then
-- Deglitched trigger delay -- Deglitched trigger delay
trig_degl_d0 <= trig_degl; trig_degl_d0 <= trig_degl;
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 00387791
...@@ -78,39 +78,38 @@ ...@@ -78,39 +78,38 @@
</files> </files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"> <transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1366299832">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363103684" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1363103684"> <transform xil_pn:end_ts="1366299833" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164504" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1363164492"> <transform xil_pn:end_ts="1366299846" xil_pn:in_ck="-88236163103343582" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1366299833">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
...@@ -125,26 +124,22 @@ ...@@ -125,26 +124,22 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1363104090" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1363104090"> <transform xil_pn:end_ts="1366299846" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1366299846">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164509" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1363164504"> <transform xil_pn:end_ts="1366299856" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1366299846">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bld"/> <outfile xil_pn:name="conv_ttl_blo_v2.bld"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164539" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1363164509"> <transform xil_pn:end_ts="1366299892" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1366299856">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pcf"/> <outfile xil_pn:name="conv_ttl_blo_v2.pcf"/>
<outfile xil_pn:name="conv_ttl_blo_v2_map.map"/> <outfile xil_pn:name="conv_ttl_blo_v2_map.map"/>
...@@ -155,11 +150,9 @@ ...@@ -155,11 +150,9 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/> <outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1363164539"> <transform xil_pn:end_ts="1366299928" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1366299892">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.ncd"/> <outfile xil_pn:name="conv_ttl_blo_v2.ncd"/>
<outfile xil_pn:name="conv_ttl_blo_v2.pad"/> <outfile xil_pn:name="conv_ttl_blo_v2.pad"/>
...@@ -171,11 +164,10 @@ ...@@ -171,11 +164,10 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/> <outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/> <outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164588" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1363164570"> <transform xil_pn:end_ts="1366299949" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1366299928">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bgn"/> <outfile xil_pn:name="conv_ttl_blo_v2.bgn"/>
<outfile xil_pn:name="conv_ttl_blo_v2.bit"/> <outfile xil_pn:name="conv_ttl_blo_v2.bit"/>
...@@ -187,18 +179,18 @@ ...@@ -187,18 +179,18 @@
<transform xil_pn:end_ts="1363164589" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363164588"> <transform xil_pn:end_ts="1363164589" xil_pn:in_ck="-7071212854459549799" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1363164588">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/> <outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/> <outfile xil_pn:name="_impact.log"/>
<outfile xil_pn:name="_impactbatch.log"/> <outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="ise_impact.cmd"/> <outfile xil_pn:name="ise_impact.cmd"/>
</transform> </transform>
<transform xil_pn:end_ts="1363164570" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1363164561"> <transform xil_pn:end_ts="1366299928" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1366299917">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twr"/> <outfile xil_pn:name="conv_ttl_blo_v2.twr"/>
<outfile xil_pn:name="conv_ttl_blo_v2.twx"/> <outfile xil_pn:name="conv_ttl_blo_v2.twx"/>
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 00387791
...@@ -127,6 +127,7 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -127,6 +127,7 @@ architecture behav of conv_ttl_blo_v2 is
port port
( (
clk_i : in std_logic; clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic rst_n_o : out std_logic
); );
end component reset_gen; end component reset_gen;
...@@ -156,6 +157,9 @@ architecture behav of conv_ttl_blo_v2 is ...@@ -156,6 +157,9 @@ architecture behav of conv_ttl_blo_v2 is
-- '0' - TYPE 2 (glitch-insensitive, with output jitter) -- '0' - TYPE 2 (glitch-insensitive, with output jitter)
pulse_type_i : in std_logic; pulse_type_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
enable_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater -- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays. -- than internal gate delays.
trig_i : in std_logic; trig_i : in std_logic;
...@@ -268,6 +272,7 @@ begin ...@@ -268,6 +272,7 @@ begin
port map port map
( (
clk_i => clk_125, clk_i => clk_125,
rst_i => '0',
rst_n_o => rst_n rst_n_o => rst_n
); );
...@@ -324,6 +329,7 @@ begin ...@@ -324,6 +329,7 @@ begin
clk_i => clk_125, clk_i => clk_125,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1), pulse_type_i => EXTRA_SWITCH(1),
enable_i => '1',
trig_i => trig(i), trig_i => trig(i),
pulse_o => pulse_outputs(i) pulse_o => pulse_outputs(i)
); );
...@@ -339,6 +345,7 @@ begin ...@@ -339,6 +345,7 @@ begin
( (
clk_i => clk_125, clk_i => clk_125,
rst_n_i => rst_n, rst_n_i => rst_n,
enable_i => '1',
pulse_type_i => EXTRA_SWITCH(1), pulse_type_i => EXTRA_SWITCH(1),
trig_i => trig(i), trig_i => trig(i),
pulse_o => pulse_leds(i) pulse_o => pulse_leds(i)
...@@ -375,6 +382,7 @@ begin ...@@ -375,6 +382,7 @@ begin
clk_i => clk_125, clk_i => clk_125,
rst_n_i => rst_n, rst_n_i => rst_n,
pulse_type_i => EXTRA_SWITCH(1), pulse_type_i => EXTRA_SWITCH(1),
enable_i => '1',
trig_i => trig_inv(i), trig_i => trig_inv(i),
pulse_o => inv_outputs(i) pulse_o => inv_outputs(i)
); );
......
hdl/vme64x_i2c/rtl/i2c_slave.vhd
View file @ 00387791
...@@ -182,6 +182,11 @@ architecture behav of i2c_slave is ...@@ -182,6 +182,11 @@ architecture behav of i2c_slave is
-- Bit counter on RX & TX -- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0); signal bit_cnt : unsigned(2 downto 0);
-- Watchdog counter signals
signal watchdog_cnt : unsigned(26 downto 0);
signal watchdog_rst : std_logic;
signal rst_fr_watchdog : std_logic;
--============================================================================== --==============================================================================
-- architecture begin -- architecture begin
--============================================================================== --==============================================================================
...@@ -277,16 +282,17 @@ begin ...@@ -277,16 +282,17 @@ begin
p_fsm: process (clk_i) is p_fsm: process (clk_i) is
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if (rst_n_i = '0') then if (rst_n_i = '0') or (rst_fr_watchdog = '1') then
state <= ST_IDLE; state <= ST_IDLE;
bit_cnt <= (others => '0'); watchdog_rst <= '1';
rxsr <= (others => '0'); bit_cnt <= (others => '0');
txsr <= (others => '0'); rxsr <= (others => '0');
sda_o <= '0'; txsr <= (others => '0');
sda_en_o <= '0'; sda_o <= '0';
done_p_o <= '0'; sda_en_o <= '0';
op_o <= '0'; done_p_o <= '0';
stat_o <= c_i2cs_idle; op_o <= '0';
stat_o <= c_i2cs_idle;
-- I2C start condition -- I2C start condition
elsif (sda_falling = '1') and (scl_degl = '1') then elsif (sda_falling = '1') and (scl_degl = '1') then
...@@ -306,11 +312,12 @@ begin ...@@ -306,11 +312,12 @@ begin
-- for a start condition. -- for a start condition.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_IDLE => when ST_IDLE =>
bit_cnt <= (others => '0'); bit_cnt <= (others => '0');
sda_o <= '0'; sda_o <= '0';
sda_en_o <= '0'; sda_en_o <= '0';
done_p_o <= '0'; done_p_o <= '0';
stat_o <= c_i2cs_idle; watchdog_rst <= '1';
stat_o <= c_i2cs_idle;
--------------------------------------------------------------------- ---------------------------------------------------------------------
-- ST_STA -- ST_STA
...@@ -320,9 +327,11 @@ begin ...@@ -320,9 +327,11 @@ begin
-- SCL, we go into the address state. -- SCL, we go into the address state.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_STA => when ST_STA =>
bit_cnt <= (others => '0'); watchdog_rst <= '0';
bit_cnt <= (others => '0');
if (scl_falling = '1') then if (scl_falling = '1') then
state <= ST_ADDR; watchdog_rst <= '1';
state <= ST_ADDR;
end if; end if;
--------------------------------------------------------------------- ---------------------------------------------------------------------
...@@ -334,10 +343,14 @@ begin ...@@ -334,10 +343,14 @@ begin
-- ADDR_ACK state. -- ADDR_ACK state.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_ADDR => when ST_ADDR =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Shifting in is done on falling edge of SCL -- Shifting in is done on falling edge of SCL
if (scl_falling = '1') then if (scl_falling = '1') then
rxsr <= rxsr(6 downto 0) & sda_degl; watchdog_rst <= '1';
bit_cnt <= bit_cnt + 1; rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1;
-- Shifted in 8 bits, go to ADDR_ACK. Check to see if received -- Shifted in 8 bits, go to ADDR_ACK. Check to see if received
-- address is ours and set op_o if so. -- address is ours and set op_o if so.
...@@ -359,6 +372,9 @@ begin ...@@ -359,6 +372,9 @@ begin
-- R/W bit received via I2C. -- R/W bit received via I2C.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_ADDR_ACK => when ST_ADDR_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Clear done pulse -- Clear done pulse
done_p_o <= '0'; done_p_o <= '0';
...@@ -371,6 +387,7 @@ begin ...@@ -371,6 +387,7 @@ begin
if (rxsr(7 downto 1) = i2c_addr_i) then if (rxsr(7 downto 1) = i2c_addr_i) then
sda_o <= ack_n_i; sda_o <= ack_n_i;
if (scl_falling = '1') then if (scl_falling = '1') then
watchdog_rst <= '1';
sda_en_o <= '0'; sda_en_o <= '0';
if (rxsr(0) = '0') then if (rxsr(0) = '0') then
state <= ST_RD; state <= ST_RD;
...@@ -390,8 +407,12 @@ begin ...@@ -390,8 +407,12 @@ begin
-- Shift in bits sent by the master. -- Shift in bits sent by the master.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_RD => when ST_RD =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Shifting occurs on falling edge of SCL -- Shifting occurs on falling edge of SCL
if (scl_falling = '1') then if (scl_falling = '1') then
watchdog_rst <= '1';
rxsr <= rxsr(6 downto 0) & sda_degl; rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1; bit_cnt <= bit_cnt + 1;
...@@ -409,6 +430,9 @@ begin ...@@ -409,6 +430,9 @@ begin
-- Send ACK/NACK, as received from external command -- Send ACK/NACK, as received from external command
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_RD_ACK => when ST_RD_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Clear done pulse -- Clear done pulse
done_p_o <= '0'; done_p_o <= '0';
...@@ -419,6 +443,7 @@ begin ...@@ -419,6 +443,7 @@ begin
-- based on the ACK received by external command, we read the next -- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK) -- bit (ACK) or go back to idle state (NACK)
if (scl_falling = '1') then if (scl_falling = '1') then
watchdog_rst <= '1';
sda_en_o <= '0'; sda_en_o <= '0';
if (ack_n_i = '0') then if (ack_n_i = '0') then
state <= ST_RD; state <= ST_RD;
...@@ -442,14 +467,17 @@ begin ...@@ -442,14 +467,17 @@ begin
-- Shift out the eight bits of TXSR. -- Shift out the eight bits of TXSR.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_WR => when ST_WR =>
watchdog_rst <= '0';
-- slave writes, so enable output -- slave writes, so enable output
sda_en_o <= '1'; sda_en_o <= '1';
sda_o <= txsr(7); sda_o <= txsr(7);
-- Shift TXSR on falling edge of SCL -- Shift TXSR on falling edge of SCL
if (scl_falling = '1') then if (scl_falling = '1') then
txsr <= txsr(6 downto 0) & '0'; watchdog_rst <= '1';
bit_cnt <= bit_cnt + 1; txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
-- Eight bits sent, disable SDA end go to WR_ACK -- Eight bits sent, disable SDA end go to WR_ACK
if (bit_cnt = 7) then if (bit_cnt = 7) then
...@@ -470,8 +498,11 @@ begin ...@@ -470,8 +498,11 @@ begin
-- state. -- state.
--------------------------------------------------------------------- ---------------------------------------------------------------------
when ST_WR_ACK => when ST_WR_ACK =>
watchdog_rst <= '0';
done_p_o <= '0'; done_p_o <= '0';
if (scl_falling = '1') then if (scl_falling = '1') then
watchdog_rst <= '1';
if (sda_degl = '0') then if (sda_degl = '0') then
state <= ST_WR_LOAD_TXSR; state <= ST_WR_LOAD_TXSR;
else else
...@@ -490,6 +521,30 @@ begin ...@@ -490,6 +521,30 @@ begin
end if; end if;
end process p_fsm; end process p_fsm;
--============================================================================
-- Watchdog counter process
-- Resets the FSM after one second. The watchdog_rst signal is controlled by
-- the FSM and resets the watchdog if the I2C master still controls the
-- slave, signaled by the SCL line going low. If for one second the master
-- does not toggle the SCL line, the FSM gets reset.
--============================================================================
p_watchdog: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (watchdog_rst = '1') then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '0';
else
watchdog_cnt <= watchdog_cnt + 1;
rst_fr_watchdog <= '0';
if (watchdog_cnt = 124999999) then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '1';
end if;
end if;
end if;
end process p_watchdog;
end architecture behav; end architecture behav;
--============================================================================== --==============================================================================
-- architecture end -- architecture end
......
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