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Removing old rtl folder.

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hdl/rtl/control/rtl/control_top.vhd deleted 100755 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:50:12 02/07/2012
-- Design Name: control_top
-- Module Name: control_top - Behavioral
-- Project Name: i2c to wishbone access controller
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the module that controls the access to the wishbone modules
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity control_top is
generic(
g_WISHBONE_MODULES : INTEGER := 6;
g_WISHBONE_MEMWIDTH : INTEGER := 32;
g_WISHBONE_ADDRWIDTH : INTEGER := 16
);
port (
-- This is a wishbone master
rst : in STD_LOGIC;
wb_master_i2c_clk : in STD_LOGIC;
wb_master_i2c_stb_o : out STD_LOGIC;
wb_master_i2c_cyc_o : out STD_LOGIC;
wb_master_i2c_sel_o : out STD_LOGIC;
wb_master_i2c_we_o : out STD_LOGIC;
wb_master_i2c_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_master_i2c_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_master_i2c_addr_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_master_i2c_ack_i : in STD_LOGIC;
wb_master_i2c_rty_i : in STD_LOGIC;
wb_master_i2c_err_i : in STD_LOGIC;
-- Interruptions
ind_wb_addr_i : in STD_LOGIC;
inst_rd_i : in STD_LOGIC;
inst_wr : in STD_LOGIC;
-- Here we add all the wishbone ports needed
wb_stb_o : out STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_cyc_o : out STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_sel_o : out STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_we_o : out STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES -1 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES -1 downto 0);
wb_addr_o : out STD_LOGIC_VECTOR (g_WISHBONE_ADDRWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_ack_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_rty_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_err_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0)
);
end control_top;
architecture Behavioral of control_top is
constant CTR0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant CTR1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant OP_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
--
-- module_number value
--
-- It is used later on on this core. It is as follows:
-- 1 i2c_slave_addr
-- 2 trigger_addr
-- 3 multiboot_addr
-- 4 EEPROM_manager_addr
-- 5 wr_core_addr
-- 6 EEPROM_memory
--
constant control_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0100";
constant i2c_slave_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0200";
constant trigger_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0300";
constant multiboot_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0400";
constant EEPROM_manager_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0500";
constant wr_core_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0600";
constant EEPROM_memory : STD_LOGIC_VECTOR (15 downto 0) := X"1000";
constant i2c_DRXA : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant i2c_DRXB : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant i2c_DTX : STD_LOGIC_VECTOR(3 downto 0) := X"6";
type FETCHER_fsm is (S0_IDLE, S1_I2C_WADDR_INT, S2_I2C_WADDR_FETCHED, S3_WB_DATA_READ, S4_I2C_WRITE_DATA, S5_DONE, S6_WB_ERROR);
type rights is array(0 to g_WISHBONE_MODULES + 1) of STD_LOGIC(1 downto 0);
signal CTRL_FETCHER_fsm : FETCHER_fsm;
signal module_right : rights;
-------------------------------------
-- STATUS register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-write
------------------------------------
-- BIT NAME Description
-- 0 GEN General ENable
-- 1 EN0 ENable access to device 0 in memory map
-- 2 EN1 ENable access to device 1 in memory map
-- 3 EN2 ENable access to device 2 in memory map
-- 4 EN3 ENable access to device 3 in memory map
-- 5 EN4 ENable access to device 4 in memory map
-- 6 EN5 ENable access to device 5 in memory map
-- 7 EN6 ENable access to device 6 in memory map
-- 8 EN7 ENable access to device 7 in memory map
-- 31-9 x Reserved
-------------------------------------
signal CTR0: STD_LOGIC_VECTOR (15 downto 0);
-------------------------------------
-- STATUS register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-write
------------------------------------
-- BIT NAME Description
-- 0 GWR General write permissions
-- 1 GRD General read permissions
-- 2 WR0 WRite permissions in memory map 0
-- 3 RD0 ReaD permissions in memory map 0
-- 4 WR1 WRite permissions in memory map 1
-- 5 RD1 ReaD permissions in memory map 1
-- 6 WR2 WRite permissions in memory map 2
-- 7 RD2 ReaD permissions in memory map 2
-- 8 WR3 WRite permissions in memory map 3
-- 9 RD3 ReaD permissions in memory map 3
-- 10 WR4 WRite permissions in memory map 4
-- 11 RD4 ReaD permissions in memory map 4
-- 12 WR5 WRite permissions in memory map 5
-- 13 RD5 ReaD permissions in memory map 5
-- 14 WR6 WRite permissions in memory map 6
-- 15 RD6 ReaD permissions in memory map 6
-- 16 WR7 WRite permissions in memory map 7
-- 17 RD7 ReaD permissions in memory map 7
-- 31-18 x Reserved
-------------------------------------
signal CTR1: STD_LOGIC_VECTOR (15 downto 0);
-------------------------------------
-- OPERATION register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
------------------------------------
-- BIT NAME Description
-- 0 RQT operation ReQuesTed
-- 1 DONE operation DONE
-- 2 ERROR operation ERROR
-- 3 WR WRite into WAO
-- 4 RD ReaD from WAO
-- 8-5 MOD wishbone MODule accessed
-- 15-9 x Reserved
-- 31-16 WAO Wishbone Address in Operation
-------------------------------------
signal OP: STD_LOGIC_VECTOR(31 downto 0);
-------------------------------------
-- Data ReaD from WishBone register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 31-0 DRD Data ReaD from WishBone
-------------------------------------
signal DRD_WB: STD_LOGIC_VECTOR(31 downto 0);
-------------------------------------
-- Data WRite to WishBone
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
------------------------------------
-- BIT NAME Description
-- 31-0 DWR Data WRite to WishBone
-------------------------------------
signal DWR_WB: STD_LOGIC_VECTOR(31 downto 0);
signal ind_address : STD_LOGIC_VECTOR(15 downto 0);
begin
gen_rights: for i in 0 to g_WISHBONE_MODULES generate
module_right(i) <= CTRL(3+2*i) & CTRL(2+2*i);
end generate gen_rights;
reg_proc: process(wb_clk)
procedure reset_control is
begin
CTR0 <= (others => '0');
CTR1 <= (others => '0');
OP <= (others => '0');
wb_master_i2c_stb_o <= '0';
wb_master_i2c_cyc_o <= '0';
wb_master_i2c_sel_o <= '0';
wb_master_i2c_we_o <= '0';
wb_master_i2c_data_o <= (others => '0');
wb_master_i2c_addr_o <= (others => '0');
-- Here we put to low the signals that interface with the rest of slaves
for i in 0 to (g_WISHBONE_MODULES - 1) loop
wb_stb_o(i) <= '0';
wb_cyc_o(i) <= '0';
wb_sel_o(i) <= '0';
wb_we_o(i) <= '0';
wb_data_o(i) <= (others => '0');
wb_addr_o(i) <= (others => '0');
end loop;
end procedure;
procedure read_i2c_reg_rqt(reg_addr: IN STD_LOGIC_VECTOR(3 downto 0) ) is
begin
wb_master_stb_o <= '1';
wb_master_cyc_o <= '1';
wb_master_we_o <= '0';
wb_master_addr_o <= reg_addr;
end procedure;
procedure read_back_i2c is
begin
if (wb_master_i2c_ack_i = '1') then
OP(31 downto 16) <= wb_master_data_i(15 downto 0);
CTRL_FETCHER_fsm <= S2_I2C_WADDR_FETCHED;
else
OP <= X"00000004";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
wb_master_stb_o <= '0';
wb_master_cyc_o <= '0';
end procedure;
procedure read_wb_reg_rqt(module_number: INTEGER) is
begin
CTRL_FETCHER_fsm <= S3_WB_DATA_READ;
OP(4 downto 0) <= "10001";
OP(8 downto 5) <= std_logic_vector(to_unsigned(module_number-1,4));
wb_stb_o(module_number) <= '1';
wb_cyc_o(module_number) <= '1';
wb_sel_o(module_number) <= '0';
wb_we_o(module_number) <= '0';
wb_addr_o(g_WISHBONE_ADDRWIDTH*module_number downto g_WISHBONE_ADDRWIDTH*(module_number-1)) <= OP(31 downto 16);
end procedure;
procedure check_address_rights is
begin
-- Check the read access
case OP(31 downto 24) is
when X"01" =>
if (module_right(0)(0) == '1')then
read_wb_reg_rqt(1);
else
end if;
when X"02" =>
if (module_right(1)(0) == '1')then
read_wb_reg_rqt(2);
else
end if;
when X"03" =>
if (module_right(2)(0) == '1')then
read_wb_reg_rqt(3);
else
end if;
when X"04" =>
if (module_right(3)(0) == '1')then
read_wb_reg_rqt(4);
else
end if;
when X"05" =>
if (module_right(4)(0) == '1')then
read_wb_reg_rqt(5);
else
end if;
when X"06" =>
if (module_right(5)(0) == '1')then
read_wb_reg_rqt(6);
else
end if;
when X"10" =>
if (module_right(6)(0) == '1')then
read_wb_reg_rq(7);
else
end if;
when others =>
end case
end procedure;
procedure write_i2c_data(data: IN STD_LOGIC_VECTOR(31 downto 0); addr: IN STD_LOGIC_VECTOR(3 downto 0)) is
begin
wb_master_i2c_stb_o <= '1';
wb_master_i2c_cyc_o <= '1';
wb_master_i2c_sel_o <= '0';
wb_master_i2c_we_o <= '1';
wb_master_i2c_data_o <= data;
wb_master_i2c_addr_o <= addr;
end procedure;
procedure wb_to_i2c is
begin
case OP(8 downto 5) is
when X"02" =>
if (wb_ack_i(0) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*1 - 1 downto 0);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*1 -1 downto 0), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when X"03" =>
if (wb_ack_i(1) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*2 -1 downto g_WISHBONE_MEMWIDTH*1);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*2 -1 downto g_WISHBONE_MEMWIDTH*1), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when X"04" =>
if (wb_ack_i(2) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*3 -1 downto g_WISHBONE_MEMWIDTH*2);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*3 -1 downto g_WISHBONE_MEMWIDTH*2), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when X"05" =>
if (wb_ack_i(3) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*4 -1 downto g_WISHBONE_MEMWIDTH*3);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*4 -1 downto g_WISHBONE_MEMWIDTH*3), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when X"06" =>
if (wb_ack_i(4) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*5 -1 downto g_WISHBONE_MEMWIDTH*4);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*5 -1 downto g_WISHBONE_MEMWIDTH*4), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when X"10" =>
if (wb_ack_i(5) = '1') then
DRD_WB <= wb_data_i(g_WISHBONE_MEMWIDTH*6 -1 downto g_WISHBONE_MEMWIDTH*5);
write_i2c_data(wb_data_i(g_WISHBONE_MEMWIDTH*6 -1 downto g_WISHBONE_MEMWIDTH*5), X"6");
CTRL_FETCHER_fsm <= S4_I2C_WRITE_DATA;
else
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end if;
when others =>
DRD_WB <= (others => '0');
OP(4 downto 0) <= "00100";
CTRL_FETCHER_fsm <= S6_WB_ERROR;
end case;
end procedure;
begin
if rising_edge(wb_clk)then
if rst = '1' then
reset_control;
elsif ind_wb_addr_i = '1' then
if CRTL_FETCHER_fsm = S0_IDLE then
CTRL_FETCHER_fsm <= S1_I2C_WADDR_INTI;
read_i2c_reg_rqt(i2c_DRXA);
else
--TODO: report this error
end if;
else
case CTRL_FETCHER is
when S0_IDLE =>
-- Nothing to do
when S1_I2C_WADDR_INT =>
-- Take care of the interrupt and perform DRXA read
read_back_i2c;
when S2_I2C_WADDR_FETCHED =>
check_address_rights;
when S3_WB_DATA_READ =>
read_back_wb;
when S4_I2C_WRITE_DATA =>
OP(4 downto 0) <= "00010";
CTRL_FETCHER_fsm <= S5_DONE;
when S5_DONE =>
OP <= (others => '0');
CTRL_FETCHER_fsm <= S0_IDLE;
when S6_WB_ERROR =>
OP <= (others => '0');
CTRL_FETCHER_fsm <= S0_IDLE;
when others =>
end case;
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/FIFO_dispatcher.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:28:55 11/08/2011
-- Design Name: FIFO dispatcher with parallel load
-- Module Name: FIFO_dispatcher - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a FIFO dispathcher with parallel load and flush.
--
-- | |
-- |----------|
-- reg_i LSB ---> | REG 0 |
-- |----------|
-- ---> | REG 1 |
-- |----------|
-- ---> | REG 2 |
-- |----------|
-- reg_i MSB ---> | REG 3 | ---> reg_o
-- |__________|
--
-- Dependencies: none
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FIFO_dispatcher is
generic(
g_data_width : NATURAL := 8;
g_dispatcher_depth : NATURAL := 4
);
port (
reg_i : in STD_LOGIC_VECTOR (g_dispatcher_depth*g_data_width-1 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
flush : in STD_LOGIC;
oen_i : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
);
end FIFO_dispatcher;
architecture Behavioral of FIFO_dispatcher is
type DISPATCHER_REG is array(0 to g_dispatcher_depth-1) of STD_LOGIC_VECTOR(g_data_width - 1 downto 0);
signal reg_int : DISPATCHER_REG;
begin
process(clk, flush)
begin
if flush = '1' then
flushLoop: for i in 0 to g_dispatcher_depth-1 loop
reg_int(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if load = '1' then
loadLoop: for i in 0 to g_dispatcher_depth - 1 loop
reg_int(i) <= reg_i((i+1)*g_data_width - 1 downto i*g_data_width) ;
end loop;
else
end if;
if oen_i = '1' then
reg_o <= reg_int(g_dispatcher_depth -1);
for i in 0 to g_dispatcher_depth - 2 loop
reg_int(i+1) <= reg_int(i);
end loop;
reg_int(0) <= (others => '0');
else
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/FIFO_stack.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 10:33:33 11/08/2011
-- Design Name: FIFO variable stack length
-- Module Name: FIFO_stack - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This module implements a generic FIFO stack of variable
-- data input length and stack depth. The ASCII art represents
-- the behaviour of the module, which works as a g_stack_depth
-- delay with parallel output
--
-- input--->
-- | |
-- |----------|
-- | REG 0 | ---> reg_o LSB
-- |----------|
-- | REG 1 | --->
-- |----------|
-- | REG 2 | --->
-- |----------|
-- | REG 3 | ---> reg_o MSB
-- |__________|
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FIFO_stack is
generic(
g_data_width : NATURAL := 8;
g_stack_depth : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
);
end FIFO_stack;
architecture Behavioral of FIFO_stack is
type FIFO_REG is array(0 to g_stack_depth-1) of std_logic_vector(g_data_width - 1 downto 0);
signal reg_int : FIFO_REG;
begin
reg_o((g_stack_depth)*g_data_width-1 downto (g_stack_depth-1)*g_data_width ) <= reg_int(g_stack_depth-1);
gen_out: for i in 0 to g_stack_depth-2 generate
reg_o((i+1)*g_data_width-1 downto i*g_data_width ) <= reg_int(i);
end generate gen_out;
reg_proc: process(clk)
begin
if rising_edge(clk) then
if flush = '1' then
for i in 0 to g_stack_depth-1 loop
reg_int(i) <= (others => '0');
end loop;
elsif push = '1' then
reg_int(0) <= reg_i;
for i in 0 to g_stack_depth-2 loop
reg_int(i+1) <= reg_int(i);
end loop;
else
end if;
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/gc_counter.vhd deleted 100755 → 0
View file @ dcfde77a
-------------------------------------------------------------------------------
-- Title : Counter with asynchronous reset
-- Project : CTDAH
-------------------------------------------------------------------------------
-- File : gc_counter.vhd
-- Author : Carlos Gil Soriano
-- Company : CERN BE-CO-HT
-- Created : 2011-07-11
-- Last update: 2011-07-11
-- Platform : FPGA-generic
-- Standard : VHDL '87
------------------------------------------------------------------------------
-- Description: Counter with asynchronous reset
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-07-11 1.0 gilsoriano Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
g_data_width: NATURAL
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
);
end gc_counter;
architecture Behavioral of gc_counter is
begin
main_proc: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_data_width-1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
end if;
cnt_o <= std_logic_vector(cnt_s);
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_bit.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_bit is
generic(
g_PRESCALER : in STD_LOGIC_VECTOR (15 downto 0) := X"0032"
);
port (
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
presc_e : in STD_LOGIC;
presc : in STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC
);
end i2c_bit;
architecture Behavioral of i2c_bit is
type bit_fsm is (S0_IDLE, S1_HIGH_TMP, S2_LOW_TMP, S3_START_TMP, S4_PAUSE_TMP, Q4_ERROR);
constant c_MAX_GLITCH_DELAY : UNSIGNED (3 downto 0) := "0110";
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111"; -- Three delay stages out of six
component counter_16
port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
sclr : in STD_LOGIC;
sset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component i2c_debouncer
generic (
g_LENGTH : UNSIGNED(3 downto 0) := c_MAX_GLITCH_DELAY;
g_outputONrise : BOOLEAN := TRUE
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end component;
component gc_ff
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
signal sda_s : STD_LOGIC;
signal scl_s : STD_LOGIC;
signal scl_saux : STD_LOGIC;
signal i2c_bit_fsm : bit_fsm;
signal scl_s_d0 : STD_LOGIC;
signal sda_s_d0 : STD_LOGIC;
signal last_scl_s : STD_LOGIC;
signal last_sda_s : STD_LOGIC;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
signal start_s : STD_LOGIC;
signal pause_s : STD_LOGIC;
signal rcved_s : STD_LOGIC;
signal presc_count : STD_LOGIC_VECTOR (15 downto 0);
signal prescaler : STD_LOGIC_VECTOR(15 downto 0);
signal presc_ce_s : STD_LOGIC;
signal sclr_s : STD_LOGIC;
signal sclr_s_d0 : STD_LOGIC;
signal sclr : STD_LOGIC;
signal sset_s : STD_LOGIC;
signal q : STD_LOGIC;
begin
--start_o <= start_s;
--pause_o <= pause_s;
--rcved_o <= rcved_s;
--done <= scl_falling;
inst_counter_16: counter_16
port map (
clk => wb_clk_i,
ce => presc_ce_s,
sclr => sclr,
sset => sset_s,
q => presc_count
);
debouncer_scl_i: i2c_debouncer
generic map(
g_outputONrise => TRUE
)
port map(
rst => rst_i,
clk => wb_clk_i,
input => scl_i,
output => scl_s,
glitch_mask => c_GLITCH_MASK
);
ff1_scl : gc_ff
port map(
Q => scl_s_d0,
C => wb_clk_i,
CLR => rst_i,
D => scl_s
);
ff2_scl : gc_ff
port map(
Q => last_scl_s,
C => wb_clk_i,
CLR => rst_i,
D => scl_s_d0
);
debouncer_sda_i: i2c_debouncer
generic map(
g_outputONrise => TRUE
)
port map(
rst => rst_i,
clk => wb_clk_i,
input => sda_i,
output => sda_s,
glitch_mask => c_GLITCH_MASK
);
ff1_sda : gc_ff
port map(
Q => sda_s_d0,
C => wb_clk_i,
CLR => rst_i,
D => sda_s
);
ff2_sda : gc_ff
port map(
Q => last_sda_s,
C => wb_clk_i,
CLR => rst_i,
D => sda_s_d0
);
process (wb_clk_i)
procedure reset_proc is
begin
i2c_bit_fsm <= S0_IDLE;
start_s <= '0';
pause_s <= '0';
rcved_s <= '1';
-- Added to solve problems in upper levels
start_o <= '0';
pause_o <= '0';
rcved_o <= '1';
--
scl_rising <= '0';
scl_falling <= '0';
done <= '0';
sset_s <= '0';
sclr_s <= '0';
end reset_proc;
procedure check_fsm is
begin
case scl_s is
when '1' =>
case i2c_bit_fsm is
when S0_IDLE =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S1_HIGH_TMP;
-- start_s <= '0';
-- pause_s <= '0';
-- rcved_s <= '1';
start_o <= '0';
pause_o <= '0';
rcved_o <= '1';
when others =>
i2c_bit_fsm <= S2_LOW_TMP;
-- start_s <= '0';
-- pause_s <= '0';
-- rcved_s <= '0';
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
end case;
when S1_HIGH_TMP =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S1_HIGH_TMP;
when others =>
i2c_bit_fsm <= S3_START_TMP;
-- start_s <= '1';
start_o <= '1';
end case;
when S2_LOW_TMP =>
case sda_s is
when '0' =>
i2c_bit_fsm <= S2_LOW_TMP;
when others =>
i2c_bit_fsm <= S4_PAUSE_TMP;
-- pause_s <= '1';
pause_o <= '1';
end case;
when S3_START_TMP =>
case sda_s is
when '0' =>
i2c_bit_fsm <= S3_START_TMP;
when others =>
i2c_bit_fsm <= Q4_ERROR;
end case;
when S4_PAUSE_TMP =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S4_PAUSE_TMP;
when others =>
i2c_bit_fsm <= Q4_ERROR;
end case;
when Q4_ERROR =>
-- start_s <= '1';
-- pause_s <= '1';
start_o <= '1';
pause_o <= '1';
end case;
when others =>
end case;
end check_fsm;
begin
-- TODO: Solve these lines to make it synthesizable
-- if presc_count = prescaler then
-- sclr_s <= '1';
---- sclr_o <= '1';
-- else
-- sclr_s <= '0';
---- sclr_o <= '0';
-- end if;
--
-- if presc_e = '1' then
-- prescaler <= presc;
-- else
-- end if;
if rising_edge(wb_clk_i) then
if rst_i = '1' then
reset_proc;
prescaler <= g_PRESCALER;
-- elsif (rising_edge(scl_s) or falling_edge(scl_s)) then
elsif (scl_s_d0 xor scl_s) = '1' then
if scl_s = '1' then
scl_rising <= '1';
else
scl_falling <= '1';
done <= '1';
end if;
check_fsm;
elsif scl_falling = '1' then
reset_proc;
elsif scl_rising = '1' then
scl_rising <= '0';
check_fsm;
else
check_fsm;
end if;
else
-- if rst_i = '1' then
-- reset_proc;
-- prescaler <= g_PRESCALER;
-- else
-- end if;
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_debounce.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity i2c_debouncer is
generic (
g_LENGTH : UNSIGNED(3 downto 0) := "0110";
g_outputONrise : BOOLEAN := TRUE
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(to_integer(g_LENGTH)-1 downto 0);
signal output_s : std_logic;
begin
ff1: FDC
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: FDC
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to to_integer(g_LENGTH)-1 generate
D_Flip_Flop : FDC
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
-- This is not VHDL 2008 to support backwards compatibility
outputFalling: if not(g_outputONrise) generate
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output_s <= '1';
elsif ( (delay_s and glitch_mask) = glitch_mask or (not(delay_s)and glitch_mask) = glitch_mask) then
output_s <= delay_s(0);
else
output_s <= '1';
end if;
else
output <= output_s;
end if;
end process;
end generate outputFalling;
outputRising: if g_outputONrise generate
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '1';
elsif ( (delay_s and glitch_mask) = glitch_mask or (not(delay_s)and glitch_mask) = glitch_mask) then
output <= delay_s(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
else
end if;
end process;
end generate outputRising;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_regs.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:56:55 10/25/2011
-- Design Name: I2C slave register HDL
-- Module Name: i2c_regs - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the HDL that holds all the register of the I2C slave
-- core
--
-- The registers should be programmed in the following order:
-- 1.- PRE Sets up the prescaler register
-- 2.- CTR0 Sets up the control register: enable, start, i2c address
-- 3.- CTR1 Sets up the threshold for detection signals in RX and TX buffers
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c_regs is
port (
-- These are the registers offers to others modules of the FPGA
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
i2c_addr : in STD_LOGIC_VECTOR (6 downto 0);
-- These are the registers that are offered to the i2c slave core
PRE_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (15 downto 0);
STA_i : in STD_LOGIC_VECTOR (15 downto 0);
DRX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX3_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX4_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX5_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX3_o : out STD_LOGIC_VECTOR (7 downto 0);
-- Controls for FIFO_dispatcher
load_TX : out STD_LOGIC;
tx_fifo_oen : out STD_LOGIC
);
end i2c_regs;
architecture Behavioral of i2c_regs is
-------------------------------------
-- STATUS register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 RST General ReSeT
-- 2 RD_WRN_INST Reserved
-- 3 A_RX
-- 4 A_TX
-- 8-5 x Reserved
-- 15-9 i2c_sla_fsm i2c fsm
-------------------------------------
constant STA_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
-------------------------------------
-- PRESCALER register
-------------------------------------
-- 16 bits
-- Wishbone access: Write-read
------------------------------------
-- BIT NAME Description
-- 15-0 PRE Prescaler value
-------------------------------------
constant PRE_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
-------------------------------------
-- CTR0 register
-------------------------------------
-- 16 bits
-- Wishbone access: Write-read
------------------------------------
-- BIT NAME Description
-- 0 EN general ENable
-- 1 RST ReSeT
-- 2 PEN Prescaler ENable
-- 5-3 x Reserved
-- 7-6 BIA Bytes Indirect Addressing
-- 14-8 A[6:0] I2c address
-- 15 x Reserved
-------------------------------------
constant CTR0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
-------------------------------------
-- CTR1 register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 RDS fsm status ReaD Status
-- 15-8 WRS fsm status WRite Status
-------------------------------------
constant CTR1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"3";
-------------------------------------
-- DRXA register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 DRX0 Data RX register 0
-- 15-8 DRX1 Data RX register 1
-- 23-16 DRX2 Data RX register 2
-- 31-24 DRX3 Data RX register 3
-------------------------------------
constant DRXA_addr : STD_LOGIC_VECTOR(3 downto 0) := X"4";
-------------------------------------
-- DRXB register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 DRX5 Data RX register 5
-- 15-8 DRX6 Data RX register 6
-- 31-16 x Reserved
-------------------------------------
constant DRXB_addr : STD_LOGIC_VECTOR(3 downto 0) := X"5";
-------------------------------------
-- DTX register
-------------------------------------
-- 16 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 7-0 RDS fsm status ReaD Status
-- 15-8 WRS fsm status WRite Status
-------------------------------------
constant DTX_addr : STD_LOGIC_VECTOR(3 downto 0) := X"6";
signal wb_ack_s : STD_LOGIC;
signal wb_rty_s : STD_LOGIC;
signal wb_err_s : STD_LOGIC;
signal STA_s : STD_LOGIC_VECTOR (15 downto 0);
signal PRE_s : STD_LOGIC_VECTOR (15 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (7 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (15 downto 0);
signal DTX0_s : STD_LOGIC_VECTOR(7 downto 0);
signal DTX1_s : STD_LOGIC_VECTOR(7 downto 0);
signal DTX2_s : STD_LOGIC_VECTOR(7 downto 0);
signal DTX3_s : STD_LOGIC_VECTOR(7 downto 0);
signal load_TX_s : STD_LOGIC;
signal tx_fifo_oen_s : STD_LOGIC;
begin
PRE_o <= PRE_s;
CTR0_o(15) <= '0';
CTR0_o(14 downto 8) <= i2c_addr;
CTR0_o(7 downto 0) <= CTR0_s;
CTR1_o <= CTR1_s;
DTX0_o <= DTX0_s;
DTX1_o <= DTX1_s;
DTX2_o <= DTX2_s;
DTX3_o <= DTX3_s;
wb_ack_o <= wb_ack_s;
wb_rty_o <= wb_rty_s;
wb_err_o <= wb_err_s;
load_TX <= load_TX_s;
tx_fifo_oen <= tx_fifo_oen_s;
process (wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
wb_data_o <= (others => '0');
wb_ack_s <= '0';
wb_rty_s <= '0';
wb_err_s <= '0';
-- This is the default maybe it is good to place the
-- autoconfiguration here.
PRE_s <= (others => '0');
CTR0_s <= (others => '0');
CTR1_s <= (others => '0');
DTX0_s <= (others => '0');
DTX1_s <= (others => '0');
DTX2_s <= (others => '0');
DTX3_s <= (others => '0');
load_TX_s <= '0';
tx_fifo_oen_s <= '0';
elsif (wb_stb_i = '1' and wb_cyc_i = '1') then
if (wb_ack_s or wb_rty_s or wb_err_s) = '1' then
wb_ack_s <= '0';
wb_rty_s <= '0';
wb_err_s <= '0';
else
case wb_we_i is
when '1' =>
case wb_addr_i is
when PRE_addr =>
PRE_s <= wb_data_i(15 downto 0);
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when CTR0_addr =>
CTR0_s <= wb_data_i(7 downto 0);
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when CTR1_addr =>
CTR1_s <= wb_data_i(15 downto 0);
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when DTX_addr =>
DTX0_s <= wb_data_i(7 downto 0);
DTX1_s <= wb_data_i(15 downto 8);
DTX2_s <= wb_data_i(23 downto 16);
DTX3_s <= wb_data_i(31 downto 24);
load_TX_s <= '1';
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when others =>
wb_ack_s <= '0';
wb_rty_s <= '0';
wb_err_s <= '1';
end case;
when others =>
case wb_addr_i is
when STA_addr =>
wb_data_o(15 downto 0) <= STA_i;
wb_data_o(31 downto 16) <= (others => '0');
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when PRE_addr =>
wb_data_o(15 downto 0) <= PRE_s;
wb_data_o(31 downto 16) <= (others => '0');
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when CTR0_addr =>
wb_data_o(7 downto 0) <= CTR0_s;
wb_data_o(14 downto 8) <= i2c_addr;
wb_data_o(31 downto 15) <= (others => '0');
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when CTR1_addr =>
wb_data_o(15 downto 0) <= CTR1_s;
wb_data_o(31 downto 16) <= (others => '0');
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when DRXA_addr =>
wb_data_o(7 downto 0) <= DRX0_i;
wb_data_o(15 downto 8) <= DRX1_i;
wb_data_o(23 downto 16) <= DRX2_i;
wb_data_o(31 downto 24) <= DRX3_i;
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when DRXB_addr =>
wb_data_o(7 downto 0) <= DRX4_i;
wb_data_o(15 downto 8) <= DRX5_i;
wb_data_o(31 downto 16) <= (others => '0');
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when DTX_addr =>
wb_data_o(7 downto 0) <= DTX0_s;
wb_data_o(15 downto 8) <= DTX1_s;
wb_data_o(23 downto 16) <= DTX2_s;
wb_data_o(31 downto 24) <= DTX3_s;
wb_ack_s <= '1';
wb_rty_s <= '0';
wb_err_s <= '0';
when others =>
wb_ack_s <= '0';
wb_rty_s <= '0';
wb_err_s <= '1';
end case;
end case;
end if;
elsif load_TX_s = '1' then
load_TX_s <= '0';
tx_fifo_oen_s <= '1';
elsif tx_fifo_oen_s = '1'then
tx_fifo_oen_s <= '0';
end if;
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge
-- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a bridge from I2C to Wishbone
--
-- Dependencies: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_slave_core is
port (
-- Wishbone port
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
-- I2C pins
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
-- Registers directly accesible
PRE_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (15 downto 0);
STA_o : out STD_LOGIC_VECTOR (15 downto 0);
DRX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX3_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX4_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX5_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX3_i : in STD_LOGIC_VECTOR (7 downto 0);
load_TX : in STD_LOGIC;
tx_fifo_oen : in STD_LOGIC;
-- Alarms for controlling the i2c states
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
end i2c_slave_core;
architecture Behavioral of i2c_slave_core is
-------------------------------------------------------------------------------
-- This is the declaration area of the constants used in other components:
-- c_PRESCALER default value of the prescaler register
-- c_COUNTER_WIDTH bit length of the gc_counter
-- c_DATA_WIDTH width of the data to be stored in FIFO_stack
-- and FIFO_dispatcher.
-- c_RX_STACK_DEPTH depth of FIFO_stack
-- c_TX_STACK_DEPTH depth of FIFO_dispatch
-------------------------------------------------------------------------------
constant c_PRESCALER : STD_LOGIC_VECTOR (15 downto 0) := X"0032";
constant c_COUNTER_WIDTH : NATURAL := 16;
constant c_DATA_WIDTH : NATURAL := 8;
constant c_RX_STACK_DEPTH : NATURAL := 6;
constant c_TX_STACK_DEPTH : NATURAL := 4;
-- fsm states of the i2c slave
type SLA_fsm is (S0_IDLE, S1_START_DETECT, S2_EVAL_FIRST_BYTE, S3_FIRST_ACKING, S4A_WRITE_SDA_BYTE, S4B_READ_SDA_BYTE, S5_FOLLOWING_ACKS, S6_PAUSE_DETECT, S7_ERROR, S8_WAIT_START_PAUSE);
signal i2c_SLA_fsm : SLA_fsm;
type RX_FIFO_REG is array(0 to c_RX_STACK_DEPTH -1) of STD_LOGIC_VECTOR(c_DATA_WIDTH -1 downto 0);
type TX_FIFO_REG is array(0 to c_TX_STACK_DEPTH -1) of STD_LOGIC_VECTOR(c_DATA_WIDTH -1 downto 0);
-------------------------------------------------------------------------------
-- i2c signals
-------------------------------------------------------------------------------
signal sda_oen_s : STD_LOGIC;
signal sda_o_s : STD_LOGIC;
signal scl_oen_s : STD_LOGIC;
signal rx_fifo_dout : RX_FIFO_REG; -- This corresponds to the six DRXi registers
signal done_s : STD_LOGIC;
signal start_o_s : STD_LOGIC;
signal pause_o_s : STD_LOGIC;
signal rcved_o_s : STD_LOGIC;
signal caseCond : STD_LOGIC_VECTOR(2 downto 0);
-- Bit counter signals
signal bit_sclr_s : STD_LOGIC;
signal bit_count_s : STD_LOGIC_VECTOR(15 downto 0);
-- RX byte counter signals
signal rx_byte_sclr_s : STD_LOGIC;
signal rx_last_bit : STD_LOGIC;
signal rx_byte_count_s: STD_LOGIC_VECTOR(15 downto 0);
-- TX byte counter signals
signal tx_byte_sclr_s : STD_LOGIC;
signal tx_last_bit : STD_LOGIC;
signal tx_byte_count_s: STD_LOGIC_VECTOR(15 downto 0);
signal tx_byte : STD_LOGIC_VECTOR(7 downto 0);
-- This is intended to be the personal address
constant i2c_general_addr : STD_LOGIC_VECTOR (6 downto 0) := "0000000";
signal i2c_addr : STD_LOGIC_VECTOR (6 downto 0);
signal i2c_general_addr_OK : BOOLEAN;
signal i2c_addr_OK : BOOLEAN;
signal i2c_rd_wrn_inst : STD_LOGIC;
signal ack_bit : STD_LOGIC;
signal rx_fifo_din : STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0);
signal rx_fifo_push : STD_LOGIC;
signal rx_fifo_flush : STD_LOGIC;
signal tx_fifo_oen_s : STD_LOGIC;
signal tx_fifo_flush : STD_LOGIC;
signal tx_fifo_reg_o : STD_LOGIC_VECTOR (c_DATA_WIDTH -1 downto 0);
signal bytes_ind_addr : STD_LOGIC_VECTOR(7 downto 6);
signal bytes_wrn_inst : STD_LOGIC_VECTOR (7 downto 0);
signal bytes_rd_inst : STD_LOGIC_VECTOR (7 downto 0);
signal alarm_ind_wb_addr : STD_LOGIC;
signal alarm_rd_inst_bytes : STD_LOGIC;
signal alarm_wrn_inst_bytes : STD_LOGIC;
component gc_counter
generic (
g_data_width : NATURAL := c_COUNTER_WIDTH
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR(g_data_width-1 downto 0)
);
end component;
component i2c_bit
generic(
g_PRESCALER : STD_LOGIC_VECTOR (15 downto 0) := c_PRESCALER
);
port (
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
presc_e : in STD_LOGIC;
presc : in STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC
);
end component;
component FIFO_stack
generic(
g_data_width : NATURAL := c_DATA_WIDTH;
g_stack_depth : NATURAL := c_RX_STACK_DEPTH
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
);
end component;
component FIFO_dispatcher
generic(
g_data_width : NATURAL := c_DATA_WIDTH;
g_dispatcher_depth : NATURAL := c_TX_STACK_DEPTH
);
port (
reg_i : in STD_LOGIC_VECTOR (c_TX_STACK_DEPTH*c_DATA_WIDTH-1 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
flush : in STD_LOGIC;
oen_i : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (c_DATA_WIDTH - 1 downto 0)
);
end component;
component gc_ff
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
begin
caseCond <= start_o_s & pause_o_s & rcved_o_s;
i2c_addr <= CTR0_i (14 downto 8);
bytes_ind_addr <= CTR0_i (7 downto 6);
bytes_wrn_inst <= CTR1_i (15 downto 8);
bytes_rd_inst <= CTR1_i (7 downto 0);
bit_counter_16: gc_counter
port map (
clk_i => wb_clk,
rst_i => bit_sclr_s or wb_rst_i,
en_i => done_s,
cnt_o => bit_count_s
);
rx_byte_counter_16: gc_counter
port map (
clk_i => wb_clk,
rst_i => rx_byte_sclr_s or wb_rst_i,
en_i => rx_last_bit,
cnt_o => rx_byte_count_s
);
tx_byte_counter_16: gc_counter
port map (
clk_i => wb_clk,
rst_i => tx_byte_sclr_s or wb_rst_i,
en_i => tx_last_bit,
cnt_o => tx_byte_count_s
);
inst_i2c_bit : i2c_bit
port map(
rst_i => wb_rst_i,
wb_clk_i => wb_clk, -- Targeted at 20 MHz
presc_e => CTR0_i(2),
presc => PRE_i,
done => done_s,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o_s,
pause_o => pause_o_s,
rcved_o => rcved_o_s
);
-- We left half a wishbone cycle for setting the data before
-- passing it to the FIFO
ff_i2c_bit0: gc_ff
port map(
Q => rx_fifo_din(0),
C => not(wb_clk) and done_s,
CLR => wb_rst_i,
D => rcved_o_s
);
ff_i2c_byte: for i in 1 to 7 generate
ff_i2c_byte: gc_ff
port map(
Q => rx_fifo_din(i),
C => not(wb_clk) and done_s,
CLR => wb_rst_i,
D => rx_fifo_din(i - 1)
);
end generate ff_i2c_byte;
rx_fifo_i2c: FIFO_stack
port map(
reg_i => rx_fifo_din,
clk => wb_clk,
push => rx_last_bit,
flush => wb_rst_i or rx_fifo_flush,
reg_o(7 downto 0) => DRX0_o,
reg_o(15 downto 8) => DRX1_o,
reg_o(23 downto 16) => DRX2_o,
reg_o(31 downto 24) => DRX3_o,
reg_o(39 downto 32) => DRX4_o,
reg_o(47 downto 40) => DRX5_o
);
tx_fifo_i2c: FIFO_dispatcher
port map(
reg_i(7 downto 0) => DTX3_i,
reg_i(15 downto 8) => DTX2_i,
reg_i(23 downto 16) => DTX1_i,
reg_i(31 downto 24) => DTX0_i,
clk => wb_clk,
load => load_TX,
flush => tx_fifo_flush,
oen_i => tx_fifo_oen OR tx_fifo_oen_s,
reg_o => tx_fifo_reg_o
);
reg_proc: process(wb_clk)
procedure write_SDA is
begin
sda_oen_s <= '0';
end procedure;
procedure read_SDA is
begin
sda_oen_s <= '1';
end procedure;
procedure reset_proc is
begin
-- First we reset the fsm
i2c_SLA_fsm <= S0_IDLE;
read_SDA;
sda_o_s <= '1';
scl_oen_s <= '1';
-- By default we do not acknowledge
ack_bit <= '1';
-- RX FIFO
rx_last_bit <= '0';
rx_fifo_flush <= '0';
i2c_rd_wrn_inst <= '0';
-- Associated RX FIFO counter
rx_byte_sclr_s <= '0';
-- TX FIFO
tx_last_bit <= '0';
tx_fifo_flush <= '0';
-- Associated TX FIFO counter
tx_byte_sclr_s <= '0';
-- Byte that it is being transmitted
tx_byte <= (others => '0');
-- Alarm conditions are resetted
alarm_ind_wb_addr <= '0';
alarm_rd_inst_bytes <= '0';
alarm_wrn_inst_bytes <= '0';
end procedure;
procedure eval_byte is
begin
case i2c_SLA_fsm is
when S1_START_DETECT =>
i2c_SLA_fsm <= S2_EVAL_FIRST_BYTE;
rx_byte_sclr_s <= '0';
rx_fifo_flush <= '0';
tx_byte_sclr_s <= '0';
tx_fifo_flush <= '0';
when S2_EVAL_FIRST_BYTE =>
-- Here the count goes with one less value, due to the effect of
-- the start condition while counting:
-- we can only tell once it happened so that there's one delay
-- in the count of the bits for the first byte.
case bit_count_s is
when X"0006" =>
if rx_fifo_din(6 downto 0) = i2c_general_addr or rx_fifo_din(6 downto 0) = i2c_addr then
ack_bit <= '0';
else
ack_bit <= '1';
end if;
when X"0007" =>
i2c_SLA_fsm <= S3_FIRST_ACKING;
i2c_rd_wrn_inst <= rx_fifo_din(0);
-- According to the specification, the maximum delay between the
-- SCL falling edge and the placement of the ACK in the bus
-- should be less than 31% of the period. So with one eigth of
-- it should be ok.
-- However, as we already have some delays in the deglitchers,
-- we will not place that timer.
write_SDA;
sda_o_s <= ack_bit;
bit_sclr_s <= '1';
when others =>
end case;
when S4B_READ_SDA_BYTE =>
case bit_count_s is
when X"0008" =>
i2c_SLA_fsm <= S5_FOLLOWING_ACKS;
write_SDA;
ack_bit <= '0';
sda_o_s <= '0';
-- Push the FIFO_stack one position
rx_last_bit <= '1';
bit_sclr_s <= '1';
if (rx_byte_count_s = X"000" & "00" & bytes_ind_addr) then
alarm_ind_wb_addr <= '1';
end if;
when others =>
end case;
when others =>
end case;
end procedure;
procedure check_rcved_data is
begin
if sda_oen_s = '1' then
case caseCond is
-- This is the start condition
when "101" =>
i2c_SLA_fsm <= S1_START_DETECT;
bit_sclr_s <= '1';
rx_byte_sclr_s <= '1';
tx_byte_sclr_s <= '1';
-- Check for indirect read
-- TODO: the generation of alarm_ind_wb_addr should be erased from
-- here. BUT do not really know what to do with the flush command.
if (rx_byte_count_s = X"000"&"00"&bytes_ind_addr ) then
alarm_ind_wb_addr <= '1';
else
rx_fifo_flush <= '1';
end if;
-- This corresponds to the stop condition
when "010" =>
i2c_SLA_fsm <= S6_PAUSE_DETECT;
bit_sclr_s <= '1';
rx_byte_sclr_s <= '1';
tx_byte_sclr_s <= '1';
-- The reception of a high and low bit
when "000" =>
eval_byte;
when "001" =>
eval_byte;
-- Same code as "100"
when "110" =>
i2c_SLA_fsm <= S7_ERROR;
when "111" =>
i2c_SLA_fsm <= S7_ERROR;
when others =>
i2c_SLA_fsm <= S0_IDLE;
end case;
else
end if;
end procedure;
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
reset_proc;
else
-- Update all outputs
sda_oen <= sda_oen_s;
sda_o <= sda_o_s;
scl_oen <= scl_oen_s;
if done_s = '1' then
case i2c_SLA_fsm is
when S0_IDLE =>
check_rcved_data;
when S1_START_DETECT =>
check_rcved_data;
when S2_EVAL_FIRST_BYTE =>
check_rcved_data;
when S3_FIRST_ACKING =>
case caseCond is
when "101" =>
i2c_SLA_fsm <= S1_START_DETECT;
read_SDA;
sda_o_s <= '1';
ack_bit <= '1';
-- Here we prepare bit_counter_16 that will be deresetted next fsm
bit_sclr_s <= '1';
rx_byte_sclr_s <= '1';
tx_byte_sclr_s <= '1';
when "010" =>
i2c_SLA_fsm <= S6_PAUSE_DETECT;
read_SDA;
bit_sclr_s <= '1';
rx_byte_sclr_s <= '1';
tx_byte_sclr_s <= '1';
ack_bit <= '1';
sda_o_s <= '1';
when others =>
case i2c_rd_wrn_inst is
when '1' =>
if ack_bit = '0' then
i2c_SLA_fsm <= S4A_WRITE_SDA_BYTE;
write_SDA;
ack_bit <= '1';
-- Start sending the first byte
sda_o_s <= tx_fifo_reg_o(0);
tx_byte <= '0' & tx_fifo_reg_o(7 downto 1);
else
i2c_SLA_fsm <= S8_WAIT_START_PAUSE;
end if;
when others =>
read_SDA;
if ack_bit = '0' then
i2c_SLA_fsm <= S4B_READ_SDA_BYTE;
ack_bit <= '1';
sda_o_s <= '1';
else
i2c_SLA_fsm <= S8_WAIT_START_PAUSE;
end if;
end case;
end case;
when S4A_WRITE_SDA_BYTE =>
case bit_count_s is
when X"0008" =>
i2c_SLA_fsm <= S5_FOLLOWING_ACKS;
read_SDA;
sda_o_s <= '0';
ack_bit <= '0';
tx_last_bit <= '1';
bit_sclr_s <= '1';
-- Shift one position the FIFO_dispatcher
tx_fifo_oen_s <= '1';
when others =>
sda_o_s <= tx_byte(0);
tx_byte <= '0' & tx_byte(7 downto 1);
end case;
when S4B_READ_SDA_BYTE =>
check_rcved_data;
when S5_FOLLOWING_ACKS =>
tx_last_bit <= '0';
bit_sclr_s <= '0';
sda_o_s <= '1';
case i2c_rd_wrn_inst is
when '1' =>
if tx_byte_count_s(7 downto 0) = bytes_rd_inst then
i2c_SLA_fsm <= S8_WAIT_START_PAUSE;
read_SDA;
ack_bit <= '1';
tx_byte_sclr_s <= '1';
alarm_rd_inst_bytes <= '1';
else
i2c_SLA_fsm <= S4A_WRITE_SDA_BYTE;
write_SDA;
ack_bit <= '1';
-- Send the following byte in memory
sda_o_s <= tx_fifo_reg_o(0);
tx_byte <= '0' & tx_fifo_reg_o(7 downto 1);
end if;
when others =>
read_SDA;
if rx_byte_count_s(7 downto 0) = bytes_wrn_inst then
i2c_SLA_fsm <= S8_WAIT_START_PAUSE;
rx_byte_sclr_s <= '1';
alarm_wrn_inst_bytes <= '1';
else
i2c_SLA_fsm <= S4B_READ_SDA_BYTE;
ack_bit <= '1';
end if;
check_rcved_data;
end case;
when S6_PAUSE_DETECT =>
check_rcved_data;
when S8_WAIT_START_PAUSE =>
check_rcved_data;
when others =>
end case;
else
bit_sclr_s <= '0';
rx_byte_sclr_s <= '0';
tx_byte_sclr_s <= '0';
alarm_rd_inst_bytes <= '0';
alarm_wrn_inst_bytes <= '0';
alarm_ind_wb_addr <= '0';
tx_last_bit <= '0';
tx_fifo_oen_s <= '0';
rx_last_bit <= '0';
end if;
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd deleted 100755 → 0
View file @ dcfde77a
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c_slave_top is
port (
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
signal PRE_s : STD_LOGIC_VECTOR (15 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (15 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (15 downto 0);
signal STA_s : STD_LOGIC_VECTOR (15 downto 0);
signal DRX0_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX1_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX2_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX3_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX4_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX5_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX0_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX1_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX2_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX3_s : STD_LOGIC_VECTOR (7 downto 0);
signal load_TX_s : STD_LOGIC;
signal tx_fifo_oen_s : STD_LOGIC;
component i2c_slave_core
port (
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
PRE_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (15 downto 0);
STA_o : out STD_LOGIC_VECTOR (15 downto 0);
DRX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX3_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX4_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX5_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX3_i : in STD_LOGIC_VECTOR (7 downto 0);
load_TX : in STD_LOGIC;
tx_fifo_oen : in STD_LOGIC;
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
end component;
component i2c_regs
port (
-- These are the registers offers to others modules of the FPGA
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
i2c_addr : in STD_LOGIC_VECTOR (6 downto 0);
-- These are the registers that are offered to the i2c slave core
STA_i : in STD_LOGIC_VECTOR (15 downto 0);
PRE_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (15 downto 0);
DRX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX3_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX4_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX5_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX3_o : out STD_LOGIC_VECTOR (7 downto 0);
load_TX : out STD_LOGIC;
tx_fifo_oen : out STD_LOGIC
);
end component;
begin
inst_i2c_slave_core: i2c_slave_core
port map(
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
sda_oen => sda_oen,
sda_i => sda_i,
sda_o => sda_o,
scl_oen => scl_oen,
scl_i => scl_i,
scl_o => scl_o,
PRE_i => PRE_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
STA_o => STA_s,
DRX0_o => DRX0_s,
DRX1_o => DRX1_s,
DRX2_o => DRX2_s,
DRX3_o => DRX3_s,
DRX4_o => DRX4_s,
DRX5_o => DRX5_s,
DTX0_i => DTX0_s,
DTX1_i => DTX1_s,
DTX2_i => DTX2_s,
DTX3_i => DTX3_s,
load_tx => load_tx_s,
tx_fifo_oen => tx_fifo_oen_s,
ind_wb_addr => ind_wb_addr,
inst_rd => inst_rd,
inst_wr => inst_wr
);
inst_i2c_regs: i2c_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
i2c_addr => "0001111",
PRE_o => PRE_s,
CTR0_o => CTR0_s,
CTR1_o => CTR1_s,
STA_i => STA_s,
DRX0_i => DRX0_s,
DRX1_i => DRX1_s,
DRX2_i => DRX2_s,
DRX3_i => DRX3_s,
DRX4_i => DRX4_s,
DRX5_i => DRX5_s,
DTX0_o => DTX0_s,
DTX1_o => DTX1_s,
DTX2_o => DTX2_s,
DTX3_o => DTX3_s,
load_tx => load_tx_s,
tx_fifo_oen => tx_fifo_oen_s
);
end Behavioral;
hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
presc_e : IN std_logic;
presc : IN std_logic_vector(15 downto 0);
done : OUT std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal presc_e : std_logic := '0';
signal presc : std_logic_vector(15 downto 0) := (others => '0');
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal done : std_logic;
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (
rst_i => rst_i,
wb_clk_i => wb_clk_i,
presc_e => presc_e,
presc => presc,
done => done,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o
);
-- procedure stop is
-- begin
-- end procedure;
--
-- procedure one is
-- begin
-- end procedure;
--
-- procedure zero is
-- begin
-- end procedure;
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
-- insert stimulus here
wait;
end process;
END;
hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 10:59:15 10/31/2011
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd
-- Project Name: i2c_slave_wb_master
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_slave_top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE std.textio.ALL;
USE ieee.numeric_std.ALL;
ENTITY i2c_slave_top_tb IS
END i2c_slave_top_tb;
ARCHITECTURE behavior OF i2c_slave_top_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_slave_top
PORT(
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
END COMPONENT;
--Inputs
signal sda_oen : std_logic;
signal sda_i : std_logic := '0';
signal sda_o : std_logic;
signal scl_oen : std_logic;
signal scl_i : std_logic := '0';
signal scl_o : std_logic;
signal wb_clk : std_logic := '0';
signal wb_rst_i : std_logic := '0';
signal wb_stb_i : std_logic := '0';
signal wb_cyc_i : std_logic := '0';
signal wb_sel_i : std_logic := '0';
signal wb_we_i : std_logic := '0';
signal wb_data_i : std_logic_vector (31 downto 0) := X"00000000";
signal wb_data_o : std_logic_vector (31 downto 0);
signal wb_addr_i : std_logic_vector (3 downto 0) := X"0";
signal wb_ack_o : std_logic;
signal wb_rty_o : std_logic;
signal wb_err_o : std_logic;
signal inst_rd : std_logic;
signal inst_wr : std_logic;
-- Clock period definitions
constant wb_clk_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
signal PRE_value : UNSIGNED(15 downto 0) := X"0032";
signal VME_crate_slot : UNSIGNED(6 downto 0) := "0001111";
signal i2c_addr : STD_LOGIC_VECTOR(6 downto 0) := not(std_logic_vector(VME_crate_slot));
signal i2c_rcved_data : STD_LOGIC_VECTOR (7 downto 0);
constant bytes_ind_addr : STD_LOGIC_VECTOR (7 downto 6) := "10";
constant bytes_wr_state : STD_LOGIC_VECTOR (7 downto 0) := X"06";
constant bytes_rd_state : STD_LOGIC_VECTOR (7 downto 0) := X"04";
constant STA_addr : STD_LOGIC_VECTOR(3 downto 0) := X"0";
constant PRE_addr : STD_LOGIC_VECTOR(3 downto 0) := X"1";
constant CTR0_addr : STD_LOGIC_VECTOR(3 downto 0) := X"2";
constant CTR1_addr : STD_LOGIC_VECTOR(3 downto 0) := X"3";
constant DRXl_addr : STD_LOGIC_VECTOR(3 downto 0) := X"4";
constant DRXh_addr : STD_LOGIC_VECTOR(3 downto 0) := X"5";
constant DTX_addr : STD_LOGIC_VECTOR(3 downto 0) := X"6";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_slave_top PORT MAP (
sda_oen => sda_oen,
sda_i => sda_i,
sda_o => sda_o,
scl_oen => scl_oen,
scl_i => scl_i,
scl_o => scl_o,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
inst_rd => inst_rd,
inst_wr => inst_wr
);
-- Clock process definitions
wb_clk_process :process
begin
wb_clk <= '1';
wait for wb_clk_period/2;
wb_clk <= '0';
wait for wb_clk_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_period*2;
wb_rst_i <= '1';
wait for wb_clk_period*2;
wb_rst_i <= '0';
wait for wb_clk_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 6 downto 0 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure rd_wrn_send(rd_wrn_bit: STD_LOGIC) is
begin
sda_i <= rd_wrn_bit;
wait for scl_i_period;
end rd_wrn_send;
procedure read_ACK (ERRORmsg: STRING; OKmsg: STRING) is
begin
wait for scl_i_period/2;
assert sda_o = '0' report ERRORmsg severity ERROR;
if (sda_o = '0') then
report OKmsg;
end if;
wait for scl_i_period/2;
end read_ACK;
procedure write_ACK(ack_bit: STD_LOGIC) is
begin
sda_i <= ack_bit;
wait for scl_i_period;
end write_ACK;
procedure write_SDA(inv_byte: STD_LOGIC_VECTOR (7 downto 0)) is
begin
for i in 0 to 7 loop
sda_i <= inv_byte(i);
wait for scl_i_period;
end loop;
end write_SDA;
procedure read_SDA is
begin
for i in 0 to 7 loop
i2c_rcved_data(i) <= sda_o;
wait for scl_i_period;
end loop;
sda_i <= '0';
wait for scl_i_period;
sda_i <= '1';
end read_SDA;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
-------------------------------------------------------------------------
-- STA register
-------------------------------------------------------------------------
procedure read_STA is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= STA_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read STA not acked" severity ERROR;
end procedure;
procedure write_STA(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= STA_addr;
wb_data_i <= data;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_err_o = '1' report "Wishbone write STA is not signaled as error" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- PRE register
-------------------------------------------------------------------------
procedure read_PRE is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= PRE_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read PRE not acked" severity ERROR;
end procedure;
procedure write_PRE(data: STD_LOGIC_VECTOR(15 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= PRE_addr;
wb_data_i(15 downto 0) <= data;
wb_data_i(31 downto 16) <= (others => '0');
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone write PRE not acked" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- CTR0 register
-------------------------------------------------------------------------
procedure read_CTR0 is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= CTR0_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read CTR0 not acked" severity ERROR;
end procedure;
procedure write_CTR0(data: STD_LOGIC_VECTOR(15 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= CTR0_addr;
wb_data_i(15 downto 0) <= data;
wb_data_i(31 downto 16) <= (others => '0');
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone write CTR0 not acked" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- CTR1 register
-------------------------------------------------------------------------
procedure read_CTR1 is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= CTR1_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read CTR1 not acked" severity ERROR;
end procedure;
procedure write_CTR1(data: STD_LOGIC_VECTOR(15 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= CTR1_addr;
wb_data_i(15 downto 0) <= data;
wb_data_i(31 downto 16) <= (others => '0');
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone write CTR1 not acked" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- DRX0, DRX1, DRX2, DRX3 agregate access registers
-------------------------------------------------------------------------
procedure read_DRXl(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DRXl_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read DRXl not acked" severity ERROR;
end procedure;
procedure write_DRXl(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DRXl_addr;
wb_data_i <= data;
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_err_o = '1' report "Wishbone write DRXl is not signaled as error" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- DRX4, DRX5 agregate access registers
-------------------------------------------------------------------------
procedure read_DRXh(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DRXh_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read DRXh not acked" severity ERROR;
end procedure;
procedure write_DRXh(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DRXh_addr;
wb_data_i <= data;
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_err_o = '1' report "Wishbone write DRXh is not signaled as error" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- DTX agregate register access
-------------------------------------------------------------------------
procedure read_DTX(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DTX_addr;
wb_we_i <= '0';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone read DTX not acked" severity ERROR;
end procedure;
procedure write_DTX(data: STD_LOGIC_VECTOR(31 downto 0)) is
begin
wait until rising_edge(wb_clk);
wb_addr_i <= DTX_addr;
wb_data_i <= data;
wb_we_i <= '1';
wb_stb_i <= '1';
wb_cyc_i <= '1';
wait for wb_clk_period*3/2;
wait until rising_edge(wb_clk);
wb_we_i <= '0';
wb_stb_i <= '0';
wb_cyc_i <= '0';
assert wb_ack_o = '1' report "Wishbone write DTX not acked" severity ERROR;
end procedure;
-------------------------------------------------------------------------
-- Procedure for correctly setting up the i2c slave
-------------------------------------------------------------------------
procedure init_cfg_i2c_slave(PRE_data: STD_LOGIC_VECTOR(15 downto 0); CTR0_data : STD_LOGIC_VECTOR(15 downto 0) ; CTR1_data : STD_LOGIC_VECTOR(15 downto 0)) is
begin
write_CTR0(CTR0_data and X"0002");
wait for wb_clk_period;
write_PRE(PRE_data);
wait for wb_clk_period;
write_CTR0(CTR0_data and X"FF00");
wait for wb_clk_period;
write_CTR1(CTR1_data);
wait for wb_clk_period;
write_CTR0(CTR0_data); -- Enough to assert enable bit
end procedure;
begin
-- ERROR list
----> ACK erros
-- 01 Instruction byte
-- 02 Internal wishbone address high byte
-- 03 Internal wishbone address low byte
wb_rst_i <= '0';
init_cond;
wait for 100ns;
----------------------------------------------------------------------------
-- i2c_slave_top initial configuration
----------------------------------------------------------------------------
rst;
init_cfg_i2c_slave(std_logic_vector(PRE_value), '0'&i2c_addr&bytes_ind_addr&"0000"&"01", bytes_wr_state&bytes_rd_state);
-- rst;
-- start;
-- addr_send("0101100"); --This address is inverted
-- addr_send("0101101"); --This address is bad address
-- addr_send("0000000"); --This is the general address
-- rd_wrn_send('1');
-- pause;
-------------------------------------------------------------------------------
-- Performing a write according to ELMA crate needs
-------------------------------------------------------------------------------
-- Placing a reset produces an error in scl. It should be solved
-- rst;
-------------------------------------------------------------------------------
-- Indirect i2c write
-------------------------------------------------------------------------------
start;
addr_send("0001111"); -- MSB first
rd_wrn_send('0');
read_ACK("ACK@01: NACK received. Sending instruction byte (i2c addres + rd_wrn bit)", "PASS -> Instruction byte ACKED");
write_SDA(X"A5"); -- inverted MSB
read_ACK("ACK@02: NACK received. Sending internal wishbone address high byte", "PASS -> Internal Wishbone Address High Byte ACKED");
write_SDA(X"5A"); -- inverted LSB
read_ACK("ACK@03: NACK received. Sending internal wishbone address low byte", "PASS -> Internal Wishbone Address Low Byte ACKED");
write_SDA("10000000"); -- inverted
read_ACK("ACK@04: NACK received. Sending 1st byte", "PASS -> 1st data byte");
write_SDA("10000000"); -- inverted
read_ACK("ACK@04: NACK received. Sending 2nd byte", "PASS -> 2nd data byte");
write_SDA("10000000"); -- inverted
read_ACK("ACK@04: NACK received. Sending 3rd byte", "PASS -> 3rd data byte");
write_SDA("10000000"); -- inverted
read_ACK("ACK@04: NACK received. Sending 4th byte", "PASS -> 4th data byte");
pause;
wait for 100*wb_clk_period;
-------------------------------------------------------------------------------
-- Indirect i2c read
-- This is divided in a write process to set the Wishbone slave and a i2c read
-------------------------------------------------------------------------------
start;
addr_send("0001111"); --This address is inverted in bit order
rd_wrn_send('0');
read_ACK("ACK@01: NACK received. Sending instruction byte (i2c addres + rd_wrn bit)", "PASS -> Instruction byte ACKED");
write_SDA("10100101"); -- inverted MSB
read_ACK("ACK@02: NACK received. Sending internal wishbone address high byte", "PASS -> Internal Wishbone Address High Byte ACKED");
write_SDA("00000000"); -- inverted LSB
read_ACK("ACK@03: NACK received. Sending internal wishbone address low byte", "PASS -> Internal Wishbone Address Low Byte ACKED");
-- At this point we must prefetch the data to be sent
write_DTX(X"DDCCBBAA");
start;
addr_send("0001111"); --This address is inverted in bit order
rd_wrn_send('1');
read_ACK("ACK@01: NACK received. Sending instruction byte (i2c addres + rd_wrn bit)", "PASS -> Instruction byte ACKED");
read_SDA;
read_SDA;
read_SDA;
read_SDA;
pause;
-- Here we should perform a restart condition
-- start;
-- addr_send("0101100"); --This address is inverted
-- rd_wrn_send('0');
-- read_ACK("ACK@01: NACK received. Sending instruction byte (i2c addres + rd_wrn bit)", "PASS -> Instruction byte ACKED");
wait;
end process;
END;
hdl/rtl/i2c_wb_access_ctrl/rtl/i2c_wb_access_ctrl.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:50:12 11/25/2011
-- Design Name: i2c_wb_access_ctrl
-- Module Name: i2c_wb_access_ctrl - Behavioral
-- Project Name: i2c to wishbone access controller
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the moduel that controls the access to the wishbone modules
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_wb_access_ctrl is
generic(
g_WISHBONE_MODULES: NATURAL := 4;
g_WISHBONE_MEMWIDTH: NATURAL := 16
);
port (
rst : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_o : out STD_LOGIC;
wb_cyc_o : out STD_LOGIC;
wb_sel_o : out STD_LOGIC;
wb_we_o : out STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_ack_i : in STD_LOGIC;
wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC;
-- Interruptions
ind_wb_addr_i : in STD_LOGIC;
inst_rd_i : in STD_LOGIC;
inst_wr : in STD_LOGIC;
-- Here we add all the wishbone ports needed
wb_cyc_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_sel_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_we_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (32*g_WISHBONE_MODULES -1 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (32*g_WISHBONE_MODULES -1 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_ack_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_rty_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_err_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0)
);
end CTDAH_top;
architecture Behavioral of CTDAH_top is
constant CTDAH_control_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0100"
constant i2c_slave_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0200";
constant trigger_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0300";
constant EEPROM_manager_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0400";
constant wr_core_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0500";
constant EEPROM_memory : STD_LOGIC_VECTOR (15 downto 0) := X"1000";
-------------------------------------------------------------------------------
-- [ 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ]
-- [ RESERVED | X | EN5 | EN4 | EN3 | EN2 | EN1 | EN0 | GEN ]
-------------------------------------------------------------------------------
-- GEN this is the general enable
-- ENi enable access to the given wishbone module
-------------------------------------------------------------------------------
signal CTRL0: STD_LOGIC_VECTOR (15 downto 0);
-------------------------------------------------------------------------------
-- [ 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ]
-- [ x | x | RD5 | WR5 | RD4 | WR4 | RD3 | WR3 | RD2 | WR2 | RD1 | WR1 | RD0 | WR0 | GRD | GWR ]
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
signal CTRL1: STD_LOGIC_VECTOR (15 downto 0);
begin
process(wb_clk)
variable caseCond0 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(3) & CTR1(2);
variable caseCond1 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(5) & CTR1(4);
variable caseCond2 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(7) & CTR1(6);
variable caseCond3 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(9) & CTR1(8);
variable caseCond4 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(11) & CTR1(10);
variable caseCond5 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(13) & CTR1(12);
begin
if rising_edge(wb_clk)then
if ind_wb_addr_i = '1' then
-- We do some prefetch depending upon permisssions
case wb_data_o(15 downto 0) is
when CTDAH_control_addr =>
if CTRL0(0) and CTRL0 (1) then
case caseCond0 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when i2c_slave_addr =>
if CTRL0(0) and CTRL0 (2) then
case caseCond1 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when trigger_addr =>
if CTRL0(0) and CTRL0 (3) then
case caseCond2 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when EEPROM_manager_addr =>
if CTRL0(0) and CTRL0 (4) then
case caseCond3 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when wr_core_addr =>
if CTRL0(0) and CTRL0 (5) then
case caseCond4 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when EEPROM_memory =>
if CTRL0(0) and CTRL0 (6) then
case caseCond5 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when others =>
end case;
else
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/ipcore_dir/RAMID_2048.asy deleted 100755 → 0
View file @ dcfde77a
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 RAMID_2048
RECTANGLE Normal 32 32 544 672
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[10:0]
PINATTR Polarity IN
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PIN 0 112 LEFT 36
PINATTR PinName dina[15:0]
PINATTR Polarity IN
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PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
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PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[10:0]
PINATTR Polarity IN
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PIN 0 592 LEFT 36
PINATTR PinName rstb
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[15:0]
PINATTR Polarity OUT
hdl/rtl/ipcore_dir/RAMID_2048.gise deleted 100755 → 0
View file @ dcfde77a
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<!-- -->
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<!-- -->
<!-- ProjectNavigator created generated project file. -->
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<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="RAMID_2048.xise"/>
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hdl/rtl/ipcore_dir/RAMID_2048.ngc deleted 100755 → 0
View file @ dcfde77a
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\ No newline at end of file
hdl/rtl/ipcore_dir/RAMID_2048.sym deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="RAMID_2048">
<symboltype>BLOCK</symboltype>
<timestamp>2011-10-16T9:20:59</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[10:0]" />
<pin polarity="Input" x="0" y="112" name="dina[15:0]" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[10:0]" />
<pin polarity="Input" x="0" y="592" name="rstb" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="368" name="doutb[15:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">RAMID_2048</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[10:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[15:0]" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[10:0]" />
<line x2="32" y1="592" y2="592" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="592" type="pin rstb" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[15:0]" />
</graph>
</symbol>
hdl/rtl/ipcore_dir/RAMID_2048.v deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file RAMID_2048.v when simulating
// the core, RAMID_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module RAMID_2048(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input rstb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of RAMID_2048 is "black_box"
endmodule
hdl/rtl/ipcore_dir/RAMID_2048.veo deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
RAMID_2048 YourInstanceName (
.clka(clka),
.wea(wea), // Bus [0 : 0]
.addra(addra), // Bus [10 : 0]
.dina(dina), // Bus [15 : 0]
.clkb(clkb),
.rstb(rstb),
.addrb(addrb), // Bus [10 : 0]
.doutb(doutb)); // Bus [15 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file RAMID_2048.v when simulating
// the core, RAMID_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMID_2048.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAMID_2048.vhd when simulating
-- the core, RAMID_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY RAMID_2048 IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
END RAMID_2048;
ARCHITECTURE RAMID_2048_a OF RAMID_2048 IS
-- synthesis translate_off
component wrapped_RAMID_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_RAMID_2048 use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_rstb => 1,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAMID_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- synthesis translate_on
END RAMID_2048_a;
hdl/rtl/ipcore_dir/RAMID_2048.vho deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component RAMID_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of RAMID_2048: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : RAMID_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file RAMID_2048.vhd when simulating
-- the core, RAMID_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMID_2048.xco deleted 100755 → 0
View file @ dcfde77a
##############################################################
#
# Xilinx Core Generator version 12.4
# Date: Sun Oct 16 09:21:46 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=RAMID_2048
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=16
CSET read_width_b=16
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=true
CSET write_depth_a=2048
CSET write_width_a=16
CSET write_width_b=16
# END Parameters
GENERATE
# CRC: cac43165
hdl/rtl/ipcore_dir/RAMID_2048.xise deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="RAMID_2048.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="RAMID_2048.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="RAMID_2048.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx25t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="RAMID_2048" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-16T11:21:49" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5D4BF8630E7563DAFB1949560352CD90" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/rtl/ipcore_dir/RAMID_2048_flist.txt deleted 100755 → 0
View file @ dcfde77a
# Output products list for <RAMID_2048>
RAMID_2048.asy
RAMID_2048.gise
RAMID_2048.ngc
RAMID_2048.sym
RAMID_2048.v
RAMID_2048.veo
RAMID_2048.vhd
RAMID_2048.vho
RAMID_2048.xco
RAMID_2048.xise
RAMID_2048_flist.txt
RAMID_2048_xmdf.tcl
_xmsgs/pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
hdl/rtl/ipcore_dir/RAMID_2048_xmdf.tcl deleted 100755 → 0
View file @ dcfde77a
# The package naming convention is <core_name>_xmdf
package provide RAMID_2048_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::RAMID_2048_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::RAMID_2048_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name RAMID_2048
}
# ::RAMID_2048_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::RAMID_2048_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module RAMID_2048
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/rtl/ipcore_dir/RAMTT_2048.asy deleted 100755 → 0
View file @ dcfde77a
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 RAMTT_2048
RECTANGLE Normal 32 32 544 672
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[10:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[127:0]
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[10:0]
PINATTR Polarity IN
LINE Normal 0 592 32 592
PIN 0 592 LEFT 36
PINATTR PinName rstb
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[127:0]
PINATTR Polarity OUT
hdl/rtl/ipcore_dir/RAMTT_2048.gise deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="RAMTT_2048.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="RAMTT_2048.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="RAMTT_2048.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="RAMTT_2048.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="RAMTT_2048.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/rtl/ipcore_dir/RAMTT_2048.ngc deleted 100755 → 0
View file @ dcfde77a
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/rtl/ipcore_dir/RAMTT_2048.sym deleted 100755 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="RAMTT_2048">
<symboltype>BLOCK</symboltype>
<timestamp>2011-10-16T9:19:0</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[10:0]" />
<pin polarity="Input" x="0" y="112" name="dina[127:0]" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[10:0]" />
<pin polarity="Input" x="0" y="592" name="rstb" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="368" name="doutb[127:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">RAMTT_2048</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[10:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[127:0]" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[10:0]" />
<line x2="32" y1="592" y2="592" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="592" type="pin rstb" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[127:0]" />
</graph>
</symbol>
hdl/rtl/ipcore_dir/RAMTT_2048.v deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file RAMTT_2048.v when simulating
// the core, RAMTT_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module RAMTT_2048(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [127 : 0] dina;
input clkb;
input rstb;
input [10 : 0] addrb;
output [127 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(128),
.C_READ_WIDTH_B(128),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(128),
.C_WRITE_WIDTH_B(128),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of RAMTT_2048 is "black_box"
endmodule
hdl/rtl/ipcore_dir/RAMTT_2048.veo deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
RAMTT_2048 YourInstanceName (
.clka(clka),
.wea(wea), // Bus [0 : 0]
.addra(addra), // Bus [10 : 0]
.dina(dina), // Bus [127 : 0]
.clkb(clkb),
.rstb(rstb),
.addrb(addrb), // Bus [10 : 0]
.doutb(doutb)); // Bus [127 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file RAMTT_2048.v when simulating
// the core, RAMTT_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMTT_2048.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAMTT_2048.vhd when simulating
-- the core, RAMTT_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY RAMTT_2048 IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(127 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(127 downto 0));
END RAMTT_2048;
ARCHITECTURE RAMTT_2048_a OF RAMTT_2048 IS
-- synthesis translate_off
component wrapped_RAMTT_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(127 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(127 downto 0));
end component;
-- Configuration specification
for all : wrapped_RAMTT_2048 use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 128,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 128,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_rstb => 1,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 128,
c_write_width_a => 128,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAMTT_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- synthesis translate_on
END RAMTT_2048_a;
hdl/rtl/ipcore_dir/RAMTT_2048.vho deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component RAMTT_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(127 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(127 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of RAMTT_2048: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : RAMTT_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file RAMTT_2048.vhd when simulating
-- the core, RAMTT_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMTT_2048.xco deleted 100755 → 0
View file @ dcfde77a
##############################################################
#
# Xilinx Core Generator version 12.4
# Date: Sun Oct 16 09:19:48 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=RAMTT_2048
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=128
CSET read_width_b=128
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=true
CSET write_depth_a=2048
CSET write_width_a=128
CSET write_width_b=128
# END Parameters
GENERATE
# CRC: 35cb3366
hdl/rtl/ipcore_dir/RAMTT_2048.xise deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="RAMTT_2048.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="RAMTT_2048.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="RAMTT_2048.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx25t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="RAMTT_2048" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-16T11:19:50" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B04F64B410F803FCDB665FDEFD2A7E95" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/rtl/ipcore_dir/RAMTT_2048_flist.txt deleted 100755 → 0
View file @ dcfde77a
# Output products list for <RAMTT_2048>
RAMTT_2048.asy
RAMTT_2048.gise
RAMTT_2048.ngc
RAMTT_2048.sym
RAMTT_2048.v
RAMTT_2048.veo
RAMTT_2048.vhd
RAMTT_2048.vho
RAMTT_2048.xco
RAMTT_2048.xise
RAMTT_2048_flist.txt
RAMTT_2048_xmdf.tcl
_xmsgs/pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
hdl/rtl/ipcore_dir/RAMTT_2048_xmdf.tcl deleted 100755 → 0
View file @ dcfde77a
# The package naming convention is <core_name>_xmdf
package provide RAMTT_2048_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::RAMTT_2048_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::RAMTT_2048_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name RAMTT_2048
}
# ::RAMTT_2048_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::RAMTT_2048_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMTT_2048_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module RAMTT_2048
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/rtl/ipcore_dir/_xmsgs/ngcbuild.xmsgs deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
hdl/rtl/ipcore_dir/_xmsgs/pn_parser.xmsgs deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/RAMID_2048.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/rtl/ipcore_dir/_xmsgs/xst.xmsgs deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="UtilitiesC" num="159" delta="old" >Message file &quot;<arg fmt="%s" index="1">usenglish/ip.msg</arg>&quot; wasn&apos;t found.
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">9</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">9</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">7</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">9</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">9</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">9</arg>x<arg fmt="%d" index="5">2048</arg> u:<arg fmt="%d" index="6">7</arg>
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 976: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 976: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_wrapper_s6.vhd" Line 490: Net &lt;<arg fmt="%s" index="1">douta_i[8]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 428: Net &lt;<arg fmt="%s" index="1">dina_pad[8]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_prim_width.vhd" Line 432: Net &lt;<arg fmt="%s" index="1">dinb_pad[8]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd" Line 1539: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"./tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd" Line 1552: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;15:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">ENB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTDBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTSBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WEA&lt;1:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WEB&lt;1:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%d" index="2">1337</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%d" index="2">1337</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%d" index="2">1337</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3010" delta="old" >&quot;<arg fmt="%s" index="1">/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/_bbx/blk_mem_gen_v4_3/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%d" index="2">1337</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
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<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB&lt;8:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
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<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">000000000</arg>).
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hdl/rtl/ipcore_dir/blk_mem_gen_readme.txt deleted 100755 → 0
View file @ dcfde77a
Core name: Xilinx LogiCORE IP Block Memory Generator
Version: 4.3
Release Date: September 21 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core,
please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory
Generator v4.3 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 12.3 support
- Soft-ECC support for Virtex-6 and Spartan-6 devices
3. SUPPORTED DEVICES
SPARTAN-3, SPARTAN-3 XA, SPARTAN-3E SPARTAN-3E XA, SPARTAN-3A, SPARTAN-3A XA,
SPARTAN-3ADSP, SPARTAN-3ADSP XA, SPARTAN-6, SPARTAN-6L, SPARTAN-6 XA
VIRTEX-4, VIRTEX-5, VIRTEX-6, VIRTEX-6L , QVIRTEX-6
QVIRTEX-4, QRVIRTEX-4, QVIRTEX-5
4. RESOLVED ISSUES
- Spartan-6 BRAM Memory collision error
- Version fixed : 4.3
1. When the user selects SDP - in Virtex-6 devices
Solution: For SDP configuration, the write_mode is set as Read_First when Common Clock is enabled otherwise the write_mode is set as Write_First
- CR 564035
5. KNOWN ISSUES
The following are known issues for v4.3 of this core at time of release:
- Virtex-6 BRAM Memory collision error
1. When the user selects TDP (write_mode= Read First)
Impact: User will have to consider collision Issue
- Spartan-6 BRAM Memory collision error
1. When the user selects TDP (write_mode= Read First)
Impact: User will have to consider collision Issue
Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with
Write Mode = Read First in conjunction with asynchronous clocking
- Power estimation figures in the datasheet are preliminary.
- Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
- Out-of-range address input can cause the core to generate X's on the DOUT bus
- AR 23744
- When the IP core is generated for Spartan-6 devices, the core should combine
two adjacent 9k BRAMs into one 18K BRAM.
- CR 526429
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support;
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support;
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support;
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2010 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
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View file @ dcfde77a
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hdl/rtl/ipcore_dir/coregen.cgp deleted 100755 → 0
View file @ dcfde77a
SET designentry = VHDL
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hdl/rtl/ipcore_dir/coregen.log deleted 100755 → 0
View file @ dcfde77a
Welcome to Xilinx CORE Generator.
Help system initialized.
Opening project file
/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/coregen.cgp.
Project, 'coregen', initialised from file
'/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/coregen.cgp
'.
Customize and GenerateCustomizing IP...
Release 12.4 - Xilinx CORE Generator IP GUI Launcher M.81d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Partition Report
XST: Design Summary
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
VHDL instantiation template already present, so not regenerating.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Customize and GenerateCustomizing IP...
Release 12.4 - Xilinx CORE Generator IP GUI Launcher M.81d (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
VHDL instantiation template already present, so not regenerating.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
Closed project file.
hdl/rtl/loggerRAM.vhd_DEPRECATED deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:27:00 10/10/2011
-- Design Name:
-- Module Name: loggerRAM - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This a RAM logger which synchronized writes and reads of
-- time-tags and pulse identificators
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity loggerRAM is
generic(
g_REPETITOR_CHANNELS : UNSIGNED(2 downto 0) := "110"
);
port (
-- Signals coming from the FIFO
dout_ID : in STD_LOGIC_VECTOR ((to_integer(g_REPETITOR_CHANNELS)-1)*31 downto 0);
dout_UTC : in STD_LOGIC_VECTOR ((to_integer(g_REPETITOR_CHANNELS)-1)*127 downto 0);
rd_en_FIFO : out STD_LOGIC_VECTOR (to_integer(g_REPETITOR_CHANNELS) -1 downto 0);
empty_FIFO : in STD_LOGIC_VECTOR (to_integer(g_REPETITOR_CHANNELS) -1 downto 0);
full_FIFO : in STD_LOGIC_VECTOR (to_integer(g_REPETITOR_CHANNELS) -1 downto 0);
-- This wishbone interface is only used for reads
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (10 downto 0)
);
end loggerRAM;
architecture Behavioral of loggerRAM is
constant c_RAMTT_SIZE : UNSIGNED(16 downto 0) := X"0400";
type WRstate is (S0_IDLE, S1_DETECT_CHANNEL, S2_FIFO_RAM_swap);
type RDstate is (S0_IDLE, S1_READ);
component NOR8
port (
O : out STD_LOGIC;
I0 : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
I4 : in STD_LOGIC;
I5 : in STD_LOGIC;
I6 : in STD_LOGIC;
I7 : in STD_LOGIC
);
end component;
component RAMTT_2048
port(
clka : in STD_LOGIC;
wena : in STD_LOGIC_VECTOR(0 downto 0);
addra : in STD_LOGIC_VECTOR (10 downto 0);
dina : in STD_LOGIC_VECTOR (127 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR (10 downto 0);
doutb : out STD_LOGIC_VECTOR (127 downto 0)
);
end component;
component RAMID_2048
port(
clka : in STD_LOGIC;
wena : in STD_LOGIC_VECTOR (0 downto 0);
addra : in STD_LOGIC_VECTOR (10 downto 0);
dina : in STD_LOGIC_VECTOR (32 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR (10 downto 0);
doutb : out STD_LOGIC_VECTOR (32 downto 0)
);
end component;
-- globalRDY is '1' if there are no FIFO contents to get
signal loggerRAM_WRstate : WRstate;
signal loggerRAM_RDstate : RDstate;
signal fetch_FIFO_s : STD_LOGIC;
signal fetchingFIFO_s : UNSIGNED (3 downto 0);
signal currentWR_addr_s : STD_LOGIC_VECTOR (10 downto 0);
signal RD_addr_s : STD_LOGIC_VECTOR (10 downto 0);
signal wena_s : STD_LOGIC_VECTOR (0 downto 0);
signal dina_RAMTT_s : STD_LOGIC_VECTOR (127 downto 0);
signal dina_RAMID_s : STD_LOGIC_VECTOR (31 downto 0);
signal doutb_RAMTT_s : STD_LOGIC_VECTOR (127 downto 0);
signal doutb_RAMID_s : STD_LOGIC_VECTOR (31 downto 0);
begin
inst_NOR8: NOR8
port map(
O => fetch_FIFO_s,
I0 => empty_FIFO(0),
I1 => empty_FIFO(1),
I2 => empty_FIFO(2),
I3 => empty_FIFO(3),
I4 => empty_FIFO(4),
I5 => empty_FIFO(5),
I6 => empty_FIFO(6),
I7 => empty_FIFO(7)
);
inst_RAMTT_2048: RAMTT_2048
port map(
clka => wb_clk,
wena => wena_s,
addra => currentWR_addr_s,
dina => dout_UTC,
clkb => wb_clk,
rstb => wb_rst_i,
addrb => RD_addr_s,
doutb => doutb_RAMTT_s
);
inst_RAMID_2048: RAMID_2048
port map(
clka => wb_clk,
wena => wena_s,
addra => currentWR_addr_s,
dina => dout_ID,
clkb => wb_clk,
rstb => wb_rst_i,
addrb => RD_addr_s,
doutb => doutb_RAMID_s
);
process (wb_clk)
begin
if rising_edge (wb_clk) then
if (wb_rst_i = '1') then
loggerRAM_WRstate <= S0_IDLE;
loggerRAM_RDstate <= S0_IDLE;
fetchingFIFO_s <= "0000";
currentWR_addr_s <= (others => '0');
RD_addr_s <= (others => '0');
wena_s <= "0";
dina_RAMTT_s <= (others => '0');
dina_RAMID_s <= (others => '0');
doutb_RAMTT_s <= (others => '0');
doutb_RAMID_s <= (others => '0');
fetch_FIFO_s <= '0';
else
-- if (wb_stb_i = '1' and wb_cyc_i = '1') then
-- if (wb_we_i = '0' and wb_addr_i /= currentWR_addr_s) then
-- Strongly dependent on the rest of the architecture
--
-- wb_ack_o <= '0';
-- wb_err_o <= '1';
-- wb_rty_o <= '0';
-- end if;
-- else
-- end if;
case loggerRAM_WRstate is
when S0_IDLE =>
if fetch_FIFO_s = '1' then
loggerRAM_WRstate <= S1_DETECT_CHANNEL;
else
end if;
when S1_DETECT_CHANNEL =>
rr_loop : for i in to_integer(g_REPETITOR_CHANNELS) to 0 loop
if (not(empty_FIFO(i))) then
rd_en_FIFO(i) <= '1';
fetchingFIFO_s <= unsigned(i);
currentWR_addr_s <= (currentWR_addr_s + 1) mod c_RAMTT_SIZE;
loggerRAM_WRstate <= S2_FIFOs_FETCHING;
exit rr_loop;
else
end if;
end loop;
when S2_FIFO_RAM_swap =>
loggerRAM_WRstate <= S0_IDLE;
end case;
case loggerRAM_RDstate is
when S0_IDLE =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE) or (loggerRAM_WRstate = S0_IDLE) ) then
RD_addr_s <= wb_addr_i;
loggerRAM_RDstate <= S1_READ_B0;
else
wb_ack_o <= '0';
wb_rty_o <= '1';
wb_err_o <= '0';
end if;
else
end if;
when S1_READ_B0 =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE) or (loggerRAM_WRstate = S0_IDLE) ) then
wb_data_o <= doutb_RAMTT_s(31 downto 0);
loggerRAM_RDstate <= S2_READ_B1;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
when S2_READ_B1 =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE) or (loggerRAM_WRstate = S0_IDLE) ) then
wb_data_o <= doutb_RAMTT_s(63 downto 32);
loggerRAM_RDstate <= S3_READ_B2;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
when S3_READ_B2 =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE) or (loggerRAM_WRstate = S0_IDLE) ) then
wb_data_o <= doutb_RAMTT_s(95 downto 64);
loggerRAM_RDstate <= S4_READ_B3;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
when S4_READ_B3 =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE) or (loggerRAM_WRstate = S0_IDLE) ) then
wb_data_o <= doutb_RAMTT_s(127 downto 96);
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
loggerRAM_RDstate <= S5_READ_B4;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
when S5_READ_B4 =>
if (wb_stb_i and wb_cyc_i and not(wb_we_i)) = '1' then
if ( ((currentWR_add_s /= wb_addr_i) and (loggerRAM_WRstate /= S0_IDLE)) or (loggerRAM_WRstate = S0_IDLE) ) then
wb_data_o <= doutb_RAMID_s;
loggerRAM_RDstate <= S0_IDLE;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
else
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end if;
when others =>
wb_ack_o <= '0';
wb_rty_o <= '0';
wb_err_o <= '1';
end case;
end if;
end if;
end process;
end Behavioral;
hdl/rtl/test/alarm_test.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:20:52 10/16/2011
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/test/alarm_test.vhd
-- Project Name: CTDAH
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alarm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY alarm_test IS
END alarm_test;
ARCHITECTURE behavior OF alarm_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alarm
PORT(
rst : IN std_logic;
clk : IN std_logic;
en : IN std_logic;
count : IN UNSIGNED(15 downto 0);
alarm_o : OUT std_logic
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal en : std_logic := '0';
signal count : UNSIGNED(15 downto 0) := (others => '0');
--Outputs
signal alarm_o : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alarm PORT MAP (
rst => rst,
clk => clk,
en => en,
count => count,
alarm_o => alarm_o
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <='0';
en <='1';
count <=X"0FFF";
wait for clk_period*10;
en <= '0';
wait for clk_period*2048;
en <='0';
-- insert stimulus here
wait;
end process;
END;
hdl/rtl/test/debouncer_test.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:05:27 10/08/2011
-- Design Name:
-- Module Name: /media/BACKUP/Xilinx/CTDAH/CTDAH/debouncer_test.vhd
-- Project Name: CTDAH
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: debouncer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY debouncer_test IS
END debouncer_test;
ARCHITECTURE behavior OF debouncer_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT debouncer
PORT(
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : in STD_LOGIC_VECTOR(5 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal input : std_logic := '0';
signal glitch_mask : STD_LOGIC_VECTOR(5 downto 0) := "111111";
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: debouncer
PORT MAP (
rst => rst,
clk => clk,
input => input,
output => output,
glitch_mask => glitch_mask
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '1';
wait for clk_period*10;
rst <= '0';
wait for clk_period*10;
input <= '1';
wait for clk_period*10;
input <= '0';
-- insert stimulus here
wait;
end process;
END;
hdl/rtl/test/monostable_test.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:13:33 10/16/2011
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/test/monostable_test.vhd
-- Project Name: CTDAH
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: monostable
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY monostable_test IS
END monostable_test;
ARCHITECTURE behavior OF monostable_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT monostable
PORT(
rst : IN std_logic;
clk : IN std_logic;
pulse_len : IN UNSIGNED(15 downto 0);
input : IN std_logic;
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal pulse_len : unsigned(15 downto 0) := X"0000";
signal input : std_logic := '0';
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: monostable PORT MAP (
rst => rst,
clk => clk,
pulse_len => pulse_len,
input => input,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
rst <= '0';
pulse_len <= X"0FFF";
input <= '1';
wait for clk_period*256;
input <= '0';
wait for clk_period*1024;
-- insert stimulus here
wait;
end process;
END;
hdl/rtl/test/trigger_test.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 23:03:04 10/16/2011
-- Design Name: HDL trigger testbench for CTDAH
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/test/trigger_test.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description: This is a testbench for CTDAH trigger circuit
--
-- VHDL Test Bench Created by ISE for module: trigger
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY trigger_test IS
END trigger_test;
ARCHITECTURE behavior OF trigger_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trigger
PORT(
input : IN std_logic;
trigger_o : OUT std_logic;
utc_i : IN std_logic_vector(127 downto 0);
wb_rst_i : IN std_logic;
wb_clk : IN std_logic;
wb_stb_i : IN std_logic;
wb_cyc_i : IN std_logic;
wb_ack_o : OUT std_logic;
wb_err_o : OUT std_logic;
wb_rty_o : OUT std_logic;
wb_we_i : IN std_logic;
wb_sel_i : IN std_logic_vector(3 downto 0);
wb_data_i : IN std_logic_vector(31 downto 0);
wb_data_o : OUT std_logic_vector(31 downto 0);
wb_addr_i : IN std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal input : std_logic := '0';
signal wb_rst_i : std_logic := '0';
signal wb_clk : std_logic := '0';
signal wb_stb_i : std_logic := '0';
signal wb_cyc_i : std_logic := '0';
signal wb_we_i : std_logic := '0';
signal wb_sel_i : std_logic_vector(3 downto 0) := (others => '0');
signal wb_data_i : std_logic_vector(31 downto 0) := (others => '0');
signal wb_addr_i : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal trigger_o : std_logic;
signal utc_i : std_logic_vector(127 downto 0);
signal wb_ack_o : std_logic;
signal wb_err_o : std_logic;
signal wb_rty_o : std_logic;
signal wb_data_o : std_logic_vector(31 downto 0);
-- Clock period definitions
constant wb_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trigger PORT MAP (
input => input,
trigger_o => trigger_o,
utc_i => utc_i,
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_ack_o => wb_ack_o,
wb_err_o => wb_err_o,
wb_rty_o => wb_rty_o,
wb_we_i => wb_we_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i
);
-- Clock process definitions
wb_clk_process :process
begin
wb_clk <= '1';
wait for wb_clk_period/2;
wb_clk <= '0';
wait for wb_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wb_rst_i <= '1';
wait for wb_clk_period*10;
wb_rst_i <= '0';
utc_i <= X"0123456789ABCDEF0123456789ABCDEF";
wait for wb_clk_period*10;
-- Read registers via wishbone
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "000000";
wait for wb_clk_period;
assert wb_data_o = X"0000DEAD"
report "E@wb_rg: Register out of range, should be DEAD"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "000100";
wait for wb_clk_period;
assert wb_data_o(5 downto 0) = "000110"
report "E@wb_rg: c_MAX_GLITCH_STAGES should be 000110"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "001000";
wait for wb_clk_period;
assert wb_data_o(5 downto 0) = "111111"
report "E@wb_rg: CURRENT_GLITCH_MASK, should be 111111"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "001100";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"003F"
report "E@wb_rg: MIN_MONOSTABLE_LENGTH, should be 64"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "010000";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"00FF"
report "E@wb_rg: MAX_MONOSTABLE_LENGTH, should be 256"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "010100";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"007F"
report "E@wb_rg: CURRENT_MONOSTABLE_LENGTH, should be 128"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
-- Write registers via wishbone
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '1';
wb_sel_i <= X"F";
wb_addr_i <= "001000";
wb_data_i(31 downto 6) <= (others => '0');
wb_data_i(5 downto 0) <= "001111";
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "001000";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"000F"
report "E@wb_rg: CURRENT_GLITCH_MASK modified, should be 16"
severity Error;
wait for wb_clk_period*2;
-- insert stimulus here
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '1';
wb_sel_i <= X"F";
wb_addr_i <= "001100";
wb_data_i(31 downto 6) <= (others => '0');
wb_data_i(5 downto 0) <= "000111";
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "001100";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"0007"
report "E@wb_rg: MIN_MONOSTABLE_LENGTH modified, should be 7"
severity Error;
wait for wb_clk_period*2;
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '1';
wb_sel_i <= X"F";
wb_addr_i <= "010100";
wb_data_i(31 downto 6) <= (others =>'0');
wb_data_i(5 downto 0) <= "001111";
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "010100";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"000F"
report "E@wb_rg: CURRENT_MONOSTABLE_LENGTH modified, should be 16"
severity Error;
wait for wb_clk_period*2;
wb_stb_i <= '0';
wb_cyc_i <= '0';
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '1';
wb_sel_i <= X"F";
wb_addr_i <= "001000";
wb_data_i(31 downto 6) <= (others => '0');
wb_data_i(5 downto 0) <= "000011";
wait for wb_clk_period*2;
wb_stb_i <= '1';
wb_cyc_i <= '1';
wb_we_i <= '0';
wb_sel_i <= X"F";
wb_addr_i <= "001000";
wait for wb_clk_period;
assert wb_data_o(15 downto 0) = X"0003"
report "E@wb_rg: CURRENT_GLITCH_MASK modified, should be 03"
severity Error;
wait for wb_clk_period*2;
input <= '1';
wait for wb_clk_period*32;
input <= '0';
wait for wb_clk_period*2048;
wait for wb_clk_period*10;
wait for wb_clk_period*1028;
wait;
end process;
END;
hdl/rtl/trigger/rtl/TT_RAMhandler.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 08:49:17 11/30/2011
-- Design Name: Time-tagging RAM handler
-- Module Name: TT_RAMhandler - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This module handles the way the RAM is accessed
--
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity TT_RAMhandler is
generic(
g_TAGS_DATA_WIDTH : INTEGER := 96
);
port (
utc_i : in STD_LOGIC_VECTOR(g_TAGS_DATA_WIDTH - 1 downto 0);
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_i : in STD_LOGIC;
ramTT_o : out STD_LOGIC_VECTOR(g_TAGS_DATA_WIDTH - 1 downto 0);
ramID_o : out STD_LOGIC_VECTOR(31 downto 0)
);
end TT_RAMhandler;
architecture Behavioral of TT_RAMhandler is
constant c_TAGS_ADDR_WIDTH : INTEGER := 8;
constant c_TAGS_ADDR_SIZE : INTEGER := 256;
constant c_RAMTT_DATA_WIDTH : INTEGER := g_TAGS_DATA_WIDTH;
constant c_RAMID_DATA_WIDTH : INTEGER := 32;
constant c_RAMBIT_DATA_WIDTH : INTEGER := 2;
signal write_tt_done_s : STD_LOGIC;
signal dout_RAMTT : STD_LOGIC_VECTOR (c_RAMTT_DATA_WIDTH - 1 downto 0);
signal dout_RAMID : STD_LOGIC_VECTOR (c_RAMID_DATA_WIDTH - 1 downto 0);
signal clkb_s : STD_LOGIC;
signal rstb_s : STD_LOGIC;
signal CWA : STD_LOGIC_VECTOR(15 downto 0);
signal CRA : STD_LOGIC_VECTOR(15 downto 0);
component gc_RAM
generic(
g_DATA_WIDTH : INTEGER;
g_ADDR_WIDTH : INTEGER;
g_ADDR_SIZE : INTEGER
);
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end component;
begin
clkb_s <= wb_clk and RAM0_i(7);
rstb_s <= wb_rst_i or STATUS_i(1) or STATUS_i(5);
RAM1_o <= CWA & CRA;
RAMTT_256: gc_RAM
generic map(
g_DATA_WIDTH => c_RAMTT_DATA_WIDTH,
g_ADDR_WIDTH => c_TAGS_ADDR_WIDTH,
g_ADDR_SIZE => c_TAGS_ADDR_SIZE
)
port map(
clka => wb_clk,
wea => RAM0_i(7),
addra => CWA(7 downto 0),
dina => utc_i,
clkb => clkb_s,
rstb => rstb_s,
addrb => CRA(7 downto 0),
doutb => dout_RAMTT
);
RAMID_256: gc_RAM
generic map(
g_DATA_WIDTH => c_RAMID_DATA_WIDTH,
g_ADDR_WIDTH => c_TAGS_ADDR_WIDTH,
g_ADDR_SIZE => c_TAGS_ADDR_SIZE
)
port map(
clka => wb_clk,
wea => RAM0_i(7),
addra => CWA(7 downto 0),
dina(15 downto 0) => (others => '0'),
dina(31 downto 16) => STATUS_i(31 downto 16),
clkb => clkb_s,
rstb => rstb_s,
addrb => CRA(7 downto 0),
doutb => dout_RAMID
);
proc_rd: process(wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' or STATUS_i(1) = '1' then
-- Trigger clear and reset
CWA <= (others => '0');
CRA <= (others => '0');
else
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/debouncer.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debouncer is
generic (
g_LENGTH : UNSIGNED(3 downto 0) := "0110"
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end debouncer;
architecture Behavioral of debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(to_integer(g_LENGTH)-1 downto 0);
component gc_ff
port (
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
begin
ff1: gc_ff
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: gc_ff
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to to_integer(g_LENGTH)-1 generate
D_Flip_Flop : gc_ff
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '0';
else
if ( (delay_s and glitch_mask) = glitch_mask) then
output <= '1';
else
output <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/gc_RAM.vhd deleted 100755 → 0
View file @ dcfde77a
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gc_RAM is
generic(
g_DATA_WIDTH : INTEGER := 32;
g_ADDR_WIDTH : INTEGER := 8;
g_ADDR_SIZE : INTEGER := 256
);
port(
clka : in STD_LOGIC;
wea : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
dina : in STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0);
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR(g_ADDR_WIDTH - 1 downto 0);
doutb : out STD_LOGIC_VECTOR(g_DATA_WIDTH - 1 downto 0)
);
end gc_RAM;
architecture Behavioural of gc_RAM is
type ram_type is array(g_ADDR_SIZE - 1 downto 0) of STD_LOGIC_VECTOR (g_DATA_WIDTH - 1 downto 0);
signal RAM: ram_type;
begin
write_proc: process (clka)
begin
if rising_edge(clka) then
if rstb = '1' then
erase_loop: for i in 0 to g_ADDR_SIZE - 1 loop
RAM(i) <= (others => '0');
end loop erase_loop;
else
RAM(conv_integer(addra)) <= dina;
end if;
else
end if;
end process;
read_proc: process (clkb)
begin
if rising_edge(clkb) then
if rstb = '1' then
doutb <= (others => '0');
elsif addrb = addra then
doutb <= dina;
else
doutb <= RAM(conv_integer(addrb));
end if;
else
end if;
end process;
end Behavioural;
hdl/rtl/trigger/rtl/gc_ff.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:26:32 10/07/2011
-- Design Name: Basic debouncer
-- Module Name: debouncer - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_ff is
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end gc_ff;
architecture Behavioral of gc_ff is
begin
reg_proc: process(C)
begin
if rising_edge(C) then
if CLR = '1' then
Q <= '0';
else
Q <= D;
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/monostable.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 16:00:11 10/12/2011
-- Design Name: Basic monostable
-- Module Name: monostable - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: A basic monostable circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity monostable is
port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(15 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC);
end monostable;
architecture Behavioral of monostable is
type fsm is (S0_WAITING, S1_OK, S2_FORBIDDEN);
signal blo_pulse_fsm : fsm;
signal count_max : UNSIGNED (16 downto 0);
signal count_max2 : UNSIGNED (16 downto 0);
signal count_s : UNSIGNED (16 downto 0);
signal write_tt_s : STD_LOGIC;
begin
process(clk)
begin
if rising_edge(clk) then
write_tt_o <= write_tt_s;
if (rst = '1') then
output <= '0';
write_tt_s <= '0';
blo_pulse_fsm <= S0_WAITING;
else
case blo_pulse_fsm is
when S0_WAITING =>
if input = '1' then
blo_pulse_fsm <= S1_OK;
count_max <= unsigned('0' & std_logic_vector(pulse_len));
count_max2 <= unsigned(std_logic_vector(pulse_len) & '0');
count_s(16 downto 1) <= (others => '0');
count_s(0) <= '1';
output <= '1';
write_tt_s <= '1';
else
end if;
when S1_OK =>
count_s <= count_s + 1;
write_tt_s <= '0';
if count_s = count_max then
blo_pulse_fsm <= S2_FORBIDDEN;
output <= '0';
else
end if;
when S2_FORBIDDEN =>
count_s <= count_s + 1;
if count_s = count_max2 then
blo_pulse_fsm <= S0_WAITING;
else
end if;
when others =>
end case;
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/trigger_core.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the wishbone trigger which receives a debounced input
-- and outputs a trigger signal for the pulse converter
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_o : out STD_LOGIC;
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end trigger_core;
architecture Behavioral of trigger_core is
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
signal deglitched_input : STD_LOGIC;
signal deglitched_input_s : STD_LOGIC;
signal monostable_input_s : STD_LOGIC;
signal count_s : STD_LOGIC_VECTOR(15 downto 0);
signal pulse_i_controlled : STD_LOGIC;
component debouncer
generic(
g_LENGTH : UNSIGNED(3 downto 0) := to_unsigned(c_MAX_GLITCH_STAGES, 4)
);
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC;
glitch_mask : in std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end component;
component monostable
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
pulse_len : in STD_LOGIC_VECTOR(15 downto 0);
write_tt_o : out STD_LOGIC;
input : in STD_LOGIC;
output : out STD_LOGIC
);
end component;
begin
count_s <= CTR0_i(30 downto 16) & '0';
pulse_i_controlled <= pulse_i and CTR0_i(0);
inst_debo: debouncer
port map(
rst => wb_rst_i,
clk => wb_clk,
input => pulse_i_controlled,
output => deglitched_input,
glitch_mask => CTR0_i(c_MAX_GLITCH_STAGES - 1 + 8 downto 8)
);
inst_mono: monostable
port map(
rst => wb_rst_i,
clk => wb_clk,
pulse_len => STATUS_i(31 downto 16),
write_tt_o => write_tt_o,
input => deglitched_input,
output => pulse_o
);
process(wb_clk)
begin
if rising_edge(wb_clk) then
if STATUS_i(0) = '1' then
deglitched_input_s <= deglitched_input;
else
end if;
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/trigger_regs.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 14:07:55 11/28/2011
-- Design Name: Trigger registers
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: Trigger module registers for interfacing easily with
-- wishbone modules
--
-----------------------------------------------------------
-- Configuration process
-----------------------------------------------------------
-- 1.- CTR0: disable EN, EN_T
-- 2.- CTR0: set CGM, CPL
-- 3.- CTR1: set MinPL, MaxPL
-- 4.- RAM0: set CLR_TT
-- 5.- CTR0: enable EN, EN_TT
-----------------------------------------------------------
-- Recommended masks to use for the steps
-- CTR0_step1 X"xxxxxxYY" where Y is "yyy0"
-- CTR0_step2 X"xxxxxxYY" where Y is "yyy0"
-- CTR1_step3 X"xxxxxxxx"
-- RAM0_step4 X"xxxxxxxZ" where Z is "zz1z"
-- CTR0_step5 X"xxxxxxYY" where Y is "yyy1"
-----------------------------------------------------------
--
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity trigger_regs is
generic(
g_MAX_GLITCH_STAGES : INTEGER := 6;
g_DEFAULT_GLITCH_MASK : UNSIGNED (5 downto 0) := (others => '1');
-- Minimum output pulse width is 1us
-- Maximum output pulse width is 2us
-- Default values are for a reference clock of 20MHz
g_MIN_PULSE_LENGTH : INTEGER := 20;
g_MAX_PULSE_LENGTH : INTEGER := 40;
g_DEFAULT_PULSE_LENGTH : INTEGER := 30
);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM0_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_o : out STD_LOGIC_VECTOR (31 downto 0);
ramTT_i : in STD_LOGIC_VECTOR (95 downto 0);
ramID_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end trigger_regs;
architecture Behavioral of trigger_regs is
type RAM_fsm is (S0_IDLE, S1_READ_B0, S2_READ_B1, S3_READ_B2, S4_READ_B3);
signal RAMstate : RAM_fsm;
-------------------------------------
-- STATUS register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 CLR General CLeaR
-- 3-2 x Reserved
-- 4 EN_TT ENable Time-Tagging
-- 5 CLR_TT CLeaR Time-Tagging
-- 7-6 x Reserved
-- 8 EMPTY RAM empty
-- 9 FULL RAM full
-- 10 WA RAM wrapped around
-- 15-11 x Reserved
-- 31-16 CPL Current Pulse Length
-------------------------------------
constant STATUS_addr : STD_LOGIC_VECTOR (2 downto 0) := "000";
-------------------------------------
-- CTR0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 0 EN General ENable
-- 1 CLR General CLeaR
-- 3-2 x Reserved
-- 4 EN_TT ENable Time-Tagging
-- 5 CLR_TT CLeaR time-tagging
-- 7-6 RDM time-tagging ReaD Mode
-- 15-8 CGM Current Glitch Mask
-- 31-16 CPL Current Pulse Length
-------------------------------------
-- TIP: CGM is used from lowest to highest
-------------------------------------
constant CTR0_addr : STD_LOGIC_VECTOR (2 downto 0) := "001";
-------------------------------------
-- CTR1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 MinPL Minimum Pulse Length
-- 31-16 MaxPL Maximum Pulse Length
-------------------------------------
constant CTR1_addr : STD_LOGIC_VECTOR (2 downto 0) := "010";
-------------------------------------
-- RAM0 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 0 EN_TT Enable Time-tagging
-- 1 CLR_TT Clear whole contents
-- 3-2 RDM time-tagging ReaD Mode
-- 4 EMPTY RAM empty
-- 5 FULL RAM full
-- 6 WA RAM Wrapped around
-- 7 RQT ReQuesT read
-- 31-8 x Reserved
-------------------------------------
constant RAM0_addr : STD_LOGIC_VECTOR (2 downto 0) := "101";
-------------------------------------
-- RAM1 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-only
-------------------------------------
-- BIT NAME Description
-- 15-0 CRA Current Read Address
-- 31-16 CWA Current Write Address
-------------------------------------
constant RAM1_addr : STD_LOGIC_VECTOR (2 downto 0) := "110";
-------------------------------------
-- RAM2 register
-------------------------------------
-- 32 bits
-- Wishbone access: Read-write
-------------------------------------
-- BIT NAME Description
-- 15-0 SA Starting address
-- 31-16 EA Ending address
-------------------------------------
constant RAM2_addr : STD_LOGIC_VECTOR (2 downto 0) := "111";
signal STATUS_reg : STD_LOGIC_VECTOR (31 downto 0);
signal CTR0_reg : STD_LOGIC_VECTOR (31 downto 0);
signal CTR1_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM0_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM1_reg : STD_LOGIC_VECTOR (31 downto 0);
signal RAM2_reg : STD_LOGIC_VECTOR (31 downto 0);
signal wb_ack_s : STD_LOGIC;
signal wb_err_s : STD_LOGIC;
signal wb_rty_s : STD_LOGIC;
signal EN : STD_LOGIC;
signal CLR : STD_LOGIC;
signal EN_TT : STD_LOGIC;
signal CLR_TT : STD_LOGIC;
signal EMPTY : STD_LOGIC;
signal FULL : STD_LOGIC;
signal WA : STD_LOGIC;
signal RDM : STD_LOGIC_VECTOR(1 downto 0);
signal CGM : STD_LOGIC_VECTOR(7 downto 0);
signal CPL : STD_LOGIC_VECTOR(15 downto 0);
signal MinPL : STD_LOGIC_VECTOR(15 downto 0);
signal MaxPL : STD_LOGIC_VECTOR(15 downto 0);
signal RQT : STD_LOGIC;
signal SA : STD_LOGIC_VECTOR(15 downto 0);
signal EA : STD_LOGIC_VECTOR(15 downto 0);
begin
STATUS_reg <= CPL & "00000" & WA & FULL & EMPTY & "00" & CLR_TT & EN_TT & "00" & CLR & EN;
CTR0_reg <= CPL & CGM & RDM & CLR_TT & EN_TT & "00" & CLR & EN;
CTR1_reg <= MaxPL & MinPL ;
RAM0_reg <= X"000000" & RQT & WA & FULL & EMPTY & RDM & CLR_TT & EN_TT;
RAM2_reg <= EA & SA;
STATUS_o <= STATUS_reg;
CTR0_o <= CTR0_reg;
CTR1_o <= CTR1_reg;
RAM0_o <= RAM0_reg;
RAM2_o <= RAM2_reg;
process(wb_clk)
begin
if rising_edge(wb_clk) then
if wb_rst_i = '1' then
RAMstate <= S0_IDLE;
EN <= '0';
CLR <= '0';
EN_TT <= '0';
CLR_TT <= '1';
EMPTY <= '1';
FULL <= '0';
WA <= '0';
RQT <= '0';
RDM <= (others => '0');
CGM <= (others => '1');
CPL <= (others => '0');
MinPL <= std_logic_vector(to_unsigned(g_MIN_PULSE_LENGTH, 16));
MaxPL <= std_logic_vector(to_unsigned(g_MAX_PULSE_LENGTH, 16));
RQT <= '0';
SA <= (others => '0');
EA <= (others => '0');
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
wb_data_o <= (others => '0');
elsif wb_stb_i = '1' and wb_cyc_i = '1' then
-- Block mode behaviour
if wb_ack_s = '1' or wb_err_s = '1' or wb_rty_s = '1' then
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '0';
wb_rty_s <= '0';
else
if wb_we_i = '0' then
case wb_addr_i (2 downto 0) is
when STATUS_addr =>
wb_data_o <= STATUS_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR0_addr =>
wb_data_o <= CTR0_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR1_addr =>
wb_data_o <= CTR1_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM0_addr =>
wb_data_o <= RAM0_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM1_addr =>
wb_data_o <= RAM1_i;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM2_addr =>
wb_data_o <= RAM2_reg;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when others =>
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '1';
wb_rty_s <= '0';
end case;
else
case wb_addr_i is
when CTR0_addr =>
EN <= wb_data_i(0);
CLR <= wb_data_i(1);
EN_TT <= wb_data_i(4);
CLR_TT <= wb_data_i(5);
RDM <= wb_data_i(7 downto 6);
-- HW protection: anticipating bad CTR0 configuration
if wb_data_i(15 downto 8) = X"00" then
CGM <= X"01";
else
CGM <= wb_data_i(15 downto 8);
end if;
CPL <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when CTR1_addr =>
MinPL <= wb_data_i(15 downto 0);
MaxPL <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM0_addr =>
EN_TT <= wb_data_i(0);
CLR_TT <= wb_data_i(1);
RDM <= wb_data_i(3 downto 2);
-- EMPTY <= wb_data_i(4);
-- FULL <= wb_data_i(5);
-- WA <= wb_data_i(6);
RQT <= wb_data_i(7);
if STATUS_reg(0) = '1' and wb_data_i(0) = '1' and wb_data_i (7) = '1' then
case RAMstate is
when S0_IDLE =>
RAMstate <= S1_READ_B0;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S1_READ_B0 =>
wb_data_o <= RAMTT_i(31 downto 0);
RAMstate <= S2_READ_B1;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S2_READ_B1 =>
wb_data_o <= RAMTT_i(63 downto 32);
RAMstate <= S3_READ_B2;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S3_READ_B2 =>
wb_data_o <= RAMTT_i(95 downto 64);
RAMstate <= S4_READ_B3;
wb_ack_o <= '0';
wb_err_o <= '0';
wb_rty_o <= '0';
when S4_READ_B3 =>
wb_data_o <= RAMID_i(31 downto 0);
RAMstate <= S0_IDLE;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
when others =>
RAMstate <= S0_IDLE;
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
end case;
else
end if;
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when RAM2_addr =>
SA <= wb_data_i(15 downto 0);
EA <= wb_data_i(31 downto 16);
wb_ack_o <= '1';
wb_err_o <= '0';
wb_rty_o <= '0';
wb_ack_s <= '1';
wb_err_s <= '0';
wb_rty_s <= '0';
when others =>
wb_ack_o <= '0';
wb_err_o <= '1';
wb_rty_o <= '0';
wb_ack_s <= '0';
wb_err_s <= '1';
wb_rty_s <= '0';
end case;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
hdl/rtl/trigger/rtl/trigger_top.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 09:58:06 10/12/2011
-- Design Name: HDL trigger top
-- Module Name: trigger - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the wishbone trigger which receives a debounced input
-- and outputs a trigger signal for the pulse converter
-- Dependencies: none
--
-- Revision:
-- Revision 0.1
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity trigger_top is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
utc_i : in STD_LOGIC_VECTOR(95 downto 0);
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0)
);
end trigger_top;
architecture Behavioral of trigger_top is
constant c_RAM_SIZE : UNSIGNED(15 downto 0) := X"0100";
constant c_MAX_GLITCH_STAGES : INTEGER := 6;
constant c_DEFAULT_GLITCH_MASK : UNSIGNED(c_MAX_GLITCH_STAGES-1 downto 0) := (others => '1');
-- Let's assume that a 20MHz clock is used in wishbone
constant c_MIN_PULSE_LENGTH : INTEGER := 20;
constant c_MAX_PULSE_LENGTH : INTEGER := 40;
constant c_DEFAULT_PULSE_LENGTH : INTEGER := 30;
constant c_TAGS_DATA_WIDTH : INTEGER := 96;
signal STATUS_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (31 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM0_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM1_s : STD_LOGIC_VECTOR (31 downto 0);
signal RAM2_s : STD_LOGIC_VECTOR (31 downto 0);
signal write_tt_s : STD_LOGIC;
signal gated_trigger_clk : STD_LOGIC;
signal gated_RAM_clk : STD_LOGIC;
signal ramTT_s : STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
signal ramID_s : STD_LOGIC_VECTOR(31 downto 0);
component trigger_regs
generic(
g_MAX_GLITCH_STAGES : INTEGER := c_MAX_GLITCH_STAGES;
g_DEFAULT_GLITCH_MASK : UNSIGNED (c_MAX_GLITCH_STAGES - 1 downto 0) := c_DEFAULT_GLITCH_MASK;
g_MIN_PULSE_LENGTH : INTEGER := c_MIN_PULSE_LENGTH;
g_MAX_PULSE_LENGTH : INTEGER := c_MAX_PULSE_LENGTH;
g_DEFAULT_PULSE_LENGTH : INTEGER := c_DEFAULT_PULSE_LENGTH
);
port (
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- Terminating signals
wb_ack_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (2 downto 0);
STATUS_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (31 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM0_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_o : out STD_LOGIC_VECTOR (31 downto 0);
ramTT_i : in STD_LOGIC_VECTOR (95 downto 0);
ramID_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component trigger_core is
port (
pulse_i : in STD_LOGIC;
pulse_o : out STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
write_tt_o : out STD_LOGIC;
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component TT_RAMhandler is
generic (
g_TAGS_DATA_WIDTH : INTEGER := 96
);
port (
utc_i : in STD_LOGIC_VECTOR(g_TAGS_DATA_WIDTH - 1 downto 0);
STATUS_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (31 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM0_i : in STD_LOGIC_VECTOR (31 downto 0);
RAM1_o : out STD_LOGIC_VECTOR (31 downto 0);
RAM2_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
write_tt_i : in STD_LOGIC;
ramTT_o : out STD_LOGIC_VECTOR(c_TAGS_DATA_WIDTH - 1 downto 0);
ramID_o : out STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
gated_trigger_clk <= wb_clk and STATUS_s(0);
gated_RAM_clk <= wb_clk and STATUS_s(0) and RAM0_s(0);
registers: trigger_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_ack_o => wb_ack_o,
wb_err_o => wb_err_o,
wb_rty_o => wb_rty_o,
wb_we_i => wb_we_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
STATUS_o => STATUS_s,
CTR0_o => CTR0_s,
CTR1_o => CTR1_s,
RAM0_o => RAM0_s,
RAM1_i => RAM1_s,
RAM2_o => RAM2_s,
ramTT_i => ramTT_s,
ramID_i => ramID_s
);
core: trigger_core
port map(
pulse_i => pulse_i,
pulse_o => pulse_o,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_o => write_tt_s,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_i => RAM1_s,
RAM2_i => RAM2_s
);
ram_handler: TT_RAMhandler
port map(
utc_i => utc_i,
STATUS_i => STATUS_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
RAM0_i => RAM0_s,
RAM1_o => RAM1_s,
RAM2_i => RAM2_s,
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
write_tt_i => write_tt_s,
ramTT_o => ramTT_s,
ramID_o => ramID_s
);
end Behavioral;
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