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Commit c7fcb65d authored by gilsoriano's avatar gilsoriano
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Removing old rtl folder.

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hdl/rtl/control/rtl/control_top.vhd deleted 100755 → 0
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hdl/rtl/i2c_slave_wb_master/rtl/FIFO_dispatcher.vhd deleted 100755 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:28:55 11/08/2011
-- Design Name: FIFO dispatcher with parallel load
-- Module Name: FIFO_dispatcher - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a FIFO dispathcher with parallel load and flush.
--
-- | |
-- |----------|
-- reg_i LSB ---> | REG 0 |
-- |----------|
-- ---> | REG 1 |
-- |----------|
-- ---> | REG 2 |
-- |----------|
-- reg_i MSB ---> | REG 3 | ---> reg_o
-- |__________|
--
-- Dependencies: none
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FIFO_dispatcher is
generic(
g_data_width : NATURAL := 8;
g_dispatcher_depth : NATURAL := 4
);
port (
reg_i : in STD_LOGIC_VECTOR (g_dispatcher_depth*g_data_width-1 downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
flush : in STD_LOGIC;
oen_i : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
);
end FIFO_dispatcher;
architecture Behavioral of FIFO_dispatcher is
type DISPATCHER_REG is array(0 to g_dispatcher_depth-1) of STD_LOGIC_VECTOR(g_data_width - 1 downto 0);
signal reg_int : DISPATCHER_REG;
begin
process(clk, flush)
begin
if flush = '1' then
flushLoop: for i in 0 to g_dispatcher_depth-1 loop
reg_int(i) <= (others => '0');
end loop;
elsif rising_edge(clk) then
if load = '1' then
loadLoop: for i in 0 to g_dispatcher_depth - 1 loop
reg_int(i) <= reg_i((i+1)*g_data_width - 1 downto i*g_data_width) ;
end loop;
else
end if;
if oen_i = '1' then
reg_o <= reg_int(g_dispatcher_depth -1);
for i in 0 to g_dispatcher_depth - 2 loop
reg_int(i+1) <= reg_int(i);
end loop;
reg_int(0) <= (others => '0');
else
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/FIFO_stack.vhd deleted 100755 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 10:33:33 11/08/2011
-- Design Name: FIFO variable stack length
-- Module Name: FIFO_stack - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This module implements a generic FIFO stack of variable
-- data input length and stack depth. The ASCII art represents
-- the behaviour of the module, which works as a g_stack_depth
-- delay with parallel output
--
-- input--->
-- | |
-- |----------|
-- | REG 0 | ---> reg_o LSB
-- |----------|
-- | REG 1 | --->
-- |----------|
-- | REG 2 | --->
-- |----------|
-- | REG 3 | ---> reg_o MSB
-- |__________|
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity FIFO_stack is
generic(
g_data_width : NATURAL := 8;
g_stack_depth : NATURAL := 8
);
port (
reg_i : in STD_LOGIC_VECTOR (g_data_width-1 downto 0);
clk : in STD_LOGIC;
push : in STD_LOGIC;
flush : in STD_LOGIC;
reg_o : out STD_LOGIC_VECTOR (g_stack_depth*g_data_width - 1 downto 0)
);
end FIFO_stack;
architecture Behavioral of FIFO_stack is
type FIFO_REG is array(0 to g_stack_depth-1) of std_logic_vector(g_data_width - 1 downto 0);
signal reg_int : FIFO_REG;
begin
reg_o((g_stack_depth)*g_data_width-1 downto (g_stack_depth-1)*g_data_width ) <= reg_int(g_stack_depth-1);
gen_out: for i in 0 to g_stack_depth-2 generate
reg_o((i+1)*g_data_width-1 downto i*g_data_width ) <= reg_int(i);
end generate gen_out;
reg_proc: process(clk)
begin
if rising_edge(clk) then
if flush = '1' then
for i in 0 to g_stack_depth-1 loop
reg_int(i) <= (others => '0');
end loop;
elsif push = '1' then
reg_int(0) <= reg_i;
for i in 0 to g_stack_depth-2 loop
reg_int(i+1) <= reg_int(i);
end loop;
else
end if;
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/gc_counter.vhd deleted 100755 → 0
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-------------------------------------------------------------------------------
-- Title : Counter with asynchronous reset
-- Project : CTDAH
-------------------------------------------------------------------------------
-- File : gc_counter.vhd
-- Author : Carlos Gil Soriano
-- Company : CERN BE-CO-HT
-- Created : 2011-07-11
-- Last update: 2011-07-11
-- Platform : FPGA-generic
-- Standard : VHDL '87
------------------------------------------------------------------------------
-- Description: Counter with asynchronous reset
-------------------------------------------------------------------------------
--
-- Copyright (c) 2009 - 2010 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-07-11 1.0 gilsoriano Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity gc_counter is
generic(
g_data_width: NATURAL
);
port (
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
en_i : in STD_LOGIC;
cnt_o : out STD_LOGIC_VECTOR (g_data_width-1 downto 0)
);
end gc_counter;
architecture Behavioral of gc_counter is
begin
main_proc: process(clk_i, rst_i)
variable cnt_s : UNSIGNED(g_data_width-1 downto 0);
begin
if rst_i = '1' then
cnt_s := (others => '0');
elsif rising_edge(clk_i) then
if en_i = '1' then
-- Increment the counter if counting is enabled
cnt_s := cnt_s + 1;
else
end if;
else
end if;
cnt_o <= std_logic_vector(cnt_s);
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_bit.vhd deleted 100755 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 00:47:34 10/26/2011
-- Design Name: i2c bit recognition fsm
-- Module Name: i2c_bit - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the fsm for the recognition of a bit
--
-- Dependencies: The inputs should be debounced: i2c_debouncer.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_bit is
generic(
g_PRESCALER : in STD_LOGIC_VECTOR (15 downto 0) := X"0032"
);
port (
rst_i : in STD_LOGIC;
wb_clk_i : in STD_LOGIC;
presc_e : in STD_LOGIC;
presc : in STD_LOGIC_VECTOR (15 downto 0);
done : out STD_LOGIC;
sda_i : in STD_LOGIC;
scl_i : in STD_LOGIC;
start_o : out STD_LOGIC;
pause_o : out STD_LOGIC;
rcved_o : out STD_LOGIC
);
end i2c_bit;
architecture Behavioral of i2c_bit is
type bit_fsm is (S0_IDLE, S1_HIGH_TMP, S2_LOW_TMP, S3_START_TMP, S4_PAUSE_TMP, Q4_ERROR);
constant c_MAX_GLITCH_DELAY : UNSIGNED (3 downto 0) := "0110";
constant c_GLITCH_MASK : STD_LOGIC_VECTOR (5 downto 0) := "000111"; -- Three delay stages out of six
component counter_16
port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
sclr : in STD_LOGIC;
sset : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(15 downto 0)
);
end component;
component i2c_debouncer
generic (
g_LENGTH : UNSIGNED(3 downto 0) := c_MAX_GLITCH_DELAY;
g_outputONrise : BOOLEAN := TRUE
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end component;
component gc_ff
port(
Q : out STD_LOGIC;
C : in STD_LOGIC;
CLR : in STD_LOGIC;
D : in STD_LOGIC
);
end component;
signal sda_s : STD_LOGIC;
signal scl_s : STD_LOGIC;
signal scl_saux : STD_LOGIC;
signal i2c_bit_fsm : bit_fsm;
signal scl_s_d0 : STD_LOGIC;
signal sda_s_d0 : STD_LOGIC;
signal last_scl_s : STD_LOGIC;
signal last_sda_s : STD_LOGIC;
signal scl_rising : STD_LOGIC;
signal scl_falling : STD_LOGIC;
signal start_s : STD_LOGIC;
signal pause_s : STD_LOGIC;
signal rcved_s : STD_LOGIC;
signal presc_count : STD_LOGIC_VECTOR (15 downto 0);
signal prescaler : STD_LOGIC_VECTOR(15 downto 0);
signal presc_ce_s : STD_LOGIC;
signal sclr_s : STD_LOGIC;
signal sclr_s_d0 : STD_LOGIC;
signal sclr : STD_LOGIC;
signal sset_s : STD_LOGIC;
signal q : STD_LOGIC;
begin
--start_o <= start_s;
--pause_o <= pause_s;
--rcved_o <= rcved_s;
--done <= scl_falling;
inst_counter_16: counter_16
port map (
clk => wb_clk_i,
ce => presc_ce_s,
sclr => sclr,
sset => sset_s,
q => presc_count
);
debouncer_scl_i: i2c_debouncer
generic map(
g_outputONrise => TRUE
)
port map(
rst => rst_i,
clk => wb_clk_i,
input => scl_i,
output => scl_s,
glitch_mask => c_GLITCH_MASK
);
ff1_scl : gc_ff
port map(
Q => scl_s_d0,
C => wb_clk_i,
CLR => rst_i,
D => scl_s
);
ff2_scl : gc_ff
port map(
Q => last_scl_s,
C => wb_clk_i,
CLR => rst_i,
D => scl_s_d0
);
debouncer_sda_i: i2c_debouncer
generic map(
g_outputONrise => TRUE
)
port map(
rst => rst_i,
clk => wb_clk_i,
input => sda_i,
output => sda_s,
glitch_mask => c_GLITCH_MASK
);
ff1_sda : gc_ff
port map(
Q => sda_s_d0,
C => wb_clk_i,
CLR => rst_i,
D => sda_s
);
ff2_sda : gc_ff
port map(
Q => last_sda_s,
C => wb_clk_i,
CLR => rst_i,
D => sda_s_d0
);
process (wb_clk_i)
procedure reset_proc is
begin
i2c_bit_fsm <= S0_IDLE;
start_s <= '0';
pause_s <= '0';
rcved_s <= '1';
-- Added to solve problems in upper levels
start_o <= '0';
pause_o <= '0';
rcved_o <= '1';
--
scl_rising <= '0';
scl_falling <= '0';
done <= '0';
sset_s <= '0';
sclr_s <= '0';
end reset_proc;
procedure check_fsm is
begin
case scl_s is
when '1' =>
case i2c_bit_fsm is
when S0_IDLE =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S1_HIGH_TMP;
-- start_s <= '0';
-- pause_s <= '0';
-- rcved_s <= '1';
start_o <= '0';
pause_o <= '0';
rcved_o <= '1';
when others =>
i2c_bit_fsm <= S2_LOW_TMP;
-- start_s <= '0';
-- pause_s <= '0';
-- rcved_s <= '0';
start_o <= '0';
pause_o <= '0';
rcved_o <= '0';
end case;
when S1_HIGH_TMP =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S1_HIGH_TMP;
when others =>
i2c_bit_fsm <= S3_START_TMP;
-- start_s <= '1';
start_o <= '1';
end case;
when S2_LOW_TMP =>
case sda_s is
when '0' =>
i2c_bit_fsm <= S2_LOW_TMP;
when others =>
i2c_bit_fsm <= S4_PAUSE_TMP;
-- pause_s <= '1';
pause_o <= '1';
end case;
when S3_START_TMP =>
case sda_s is
when '0' =>
i2c_bit_fsm <= S3_START_TMP;
when others =>
i2c_bit_fsm <= Q4_ERROR;
end case;
when S4_PAUSE_TMP =>
case sda_s is
when '1' =>
i2c_bit_fsm <= S4_PAUSE_TMP;
when others =>
i2c_bit_fsm <= Q4_ERROR;
end case;
when Q4_ERROR =>
-- start_s <= '1';
-- pause_s <= '1';
start_o <= '1';
pause_o <= '1';
end case;
when others =>
end case;
end check_fsm;
begin
-- TODO: Solve these lines to make it synthesizable
-- if presc_count = prescaler then
-- sclr_s <= '1';
---- sclr_o <= '1';
-- else
-- sclr_s <= '0';
---- sclr_o <= '0';
-- end if;
--
-- if presc_e = '1' then
-- prescaler <= presc;
-- else
-- end if;
if rising_edge(wb_clk_i) then
if rst_i = '1' then
reset_proc;
prescaler <= g_PRESCALER;
-- elsif (rising_edge(scl_s) or falling_edge(scl_s)) then
elsif (scl_s_d0 xor scl_s) = '1' then
if scl_s = '1' then
scl_rising <= '1';
else
scl_falling <= '1';
done <= '1';
end if;
check_fsm;
elsif scl_falling = '1' then
reset_proc;
elsif scl_rising = '1' then
scl_rising <= '0';
check_fsm;
else
check_fsm;
end if;
else
-- if rst_i = '1' then
-- reset_proc;
-- prescaler <= g_PRESCALER;
-- else
-- end if;
end if;
end process;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_debounce.vhd deleted 100755 → 0
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----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:11:43 10/25/2011
-- Design Name:
-- Module Name: i2c_debounce - Behavioral
-- Project Name: CTDAH
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is a I2C debouncer. The main difference is that it is
-- intended to filter out low glitches. That means the oppositive
-- from the previous version --debouncer.vhd.
-- This behaviour makes more sense compared on how I2C definition
-- resolves arbitration --conceptually the same as this module.
--
-- A '1' in the glitch_mask means that the bit should be studied.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity i2c_debouncer is
generic (
g_LENGTH : UNSIGNED(3 downto 0) := "0110";
g_outputONrise : BOOLEAN := TRUE
);
port (
rst : IN std_logic;
clk : IN std_logic;
input : IN std_logic;
output : OUT std_logic;
glitch_mask : IN std_logic_vector(to_integer(g_LENGTH)-1 downto 0)
);
end i2c_debouncer;
architecture Behavioral of i2c_debouncer is
-- Signals
signal meta_ff1 : std_logic;
signal delay_s : std_logic_vector(to_integer(g_LENGTH)-1 downto 0);
signal output_s : std_logic;
begin
ff1: FDC
port map(
Q => meta_ff1,
C => clk,
CLR => rst,
D => input
);
ff2: FDC
port map(
Q => delay_s(0),
C => clk,
CLR => rst,
D => meta_ff1
);
-- Metastability solved here
delay_line: for i in 1 to to_integer(g_LENGTH)-1 generate
D_Flip_Flop : FDC
port map (
Q => delay_s(i),
C => clk,
CLR => rst,
D => delay_s(i-1));
end generate delay_line;
-- This is not VHDL 2008 to support backwards compatibility
outputFalling: if not(g_outputONrise) generate
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output_s <= '1';
elsif ( (delay_s and glitch_mask) = glitch_mask or (not(delay_s)and glitch_mask) = glitch_mask) then
output_s <= delay_s(0);
else
output_s <= '1';
end if;
else
output <= output_s;
end if;
end process;
end generate outputFalling;
outputRising: if g_outputONrise generate
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
output <= '1';
elsif ( (delay_s and glitch_mask) = glitch_mask or (not(delay_s)and glitch_mask) = glitch_mask) then
output <= delay_s(0);
else
-- Internall pull-up of the pin
output <= '1';
end if;
else
end if;
end process;
end generate outputRising;
end Behavioral;
hdl/rtl/i2c_slave_wb_master/rtl/i2c_regs.vhd deleted 100755 → 0
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hdl/rtl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd deleted 100755 → 0
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hdl/rtl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd deleted 100755 → 0
View file @ dcfde77a
---------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 18:15:56 11/09/2011
-- Design Name: A I2C slave with wishbone slave output and interrupt for MCU
-- Module Name: i2c_slave_top - Behavioral
-- Project Name: CTDAH
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c_slave_top is
port (
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
end i2c_slave_top;
architecture Behavioral of i2c_slave_top is
signal PRE_s : STD_LOGIC_VECTOR (15 downto 0);
signal CTR0_s : STD_LOGIC_VECTOR (15 downto 0);
signal CTR1_s : STD_LOGIC_VECTOR (15 downto 0);
signal STA_s : STD_LOGIC_VECTOR (15 downto 0);
signal DRX0_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX1_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX2_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX3_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX4_s : STD_LOGIC_VECTOR (7 downto 0);
signal DRX5_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX0_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX1_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX2_s : STD_LOGIC_VECTOR (7 downto 0);
signal DTX3_s : STD_LOGIC_VECTOR (7 downto 0);
signal load_TX_s : STD_LOGIC;
signal tx_fifo_oen_s : STD_LOGIC;
component i2c_slave_core
port (
wb_clk : in STD_LOGIC;
wb_rst_i : in STD_LOGIC;
sda_oen : out STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
scl_oen : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
PRE_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR0_i : in STD_LOGIC_VECTOR (15 downto 0);
CTR1_i : in STD_LOGIC_VECTOR (15 downto 0);
STA_o : out STD_LOGIC_VECTOR (15 downto 0);
DRX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX3_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX4_o : out STD_LOGIC_VECTOR (7 downto 0);
DRX5_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX3_i : in STD_LOGIC_VECTOR (7 downto 0);
load_TX : in STD_LOGIC;
tx_fifo_oen : in STD_LOGIC;
ind_wb_addr : out STD_LOGIC;
inst_rd : out STD_LOGIC;
inst_wr : out STD_LOGIC
);
end component;
component i2c_regs
port (
-- These are the registers offers to others modules of the FPGA
wb_rst_i : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_stb_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
wb_sel_i : in STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (3 downto 0);
wb_ack_o : out STD_LOGIC;
wb_rty_o : out STD_LOGIC;
wb_err_o : out STD_LOGIC;
i2c_addr : in STD_LOGIC_VECTOR (6 downto 0);
-- These are the registers that are offered to the i2c slave core
STA_i : in STD_LOGIC_VECTOR (15 downto 0);
PRE_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR0_o : out STD_LOGIC_VECTOR (15 downto 0);
CTR1_o : out STD_LOGIC_VECTOR (15 downto 0);
DRX0_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX1_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX2_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX3_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX4_i : in STD_LOGIC_VECTOR (7 downto 0);
DRX5_i : in STD_LOGIC_VECTOR (7 downto 0);
DTX0_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX1_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX2_o : out STD_LOGIC_VECTOR (7 downto 0);
DTX3_o : out STD_LOGIC_VECTOR (7 downto 0);
load_TX : out STD_LOGIC;
tx_fifo_oen : out STD_LOGIC
);
end component;
begin
inst_i2c_slave_core: i2c_slave_core
port map(
wb_clk => wb_clk,
wb_rst_i => wb_rst_i,
sda_oen => sda_oen,
sda_i => sda_i,
sda_o => sda_o,
scl_oen => scl_oen,
scl_i => scl_i,
scl_o => scl_o,
PRE_i => PRE_s,
CTR0_i => CTR0_s,
CTR1_i => CTR1_s,
STA_o => STA_s,
DRX0_o => DRX0_s,
DRX1_o => DRX1_s,
DRX2_o => DRX2_s,
DRX3_o => DRX3_s,
DRX4_o => DRX4_s,
DRX5_o => DRX5_s,
DTX0_i => DTX0_s,
DTX1_i => DTX1_s,
DTX2_i => DTX2_s,
DTX3_i => DTX3_s,
load_tx => load_tx_s,
tx_fifo_oen => tx_fifo_oen_s,
ind_wb_addr => ind_wb_addr,
inst_rd => inst_rd,
inst_wr => inst_wr
);
inst_i2c_regs: i2c_regs
port map(
wb_rst_i => wb_rst_i,
wb_clk => wb_clk,
wb_we_i => wb_we_i,
wb_stb_i => wb_stb_i,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_data_i => wb_data_i,
wb_data_o => wb_data_o,
wb_addr_i => wb_addr_i,
wb_ack_o => wb_ack_o,
wb_rty_o => wb_rty_o,
wb_err_o => wb_err_o,
i2c_addr => "0001111",
PRE_o => PRE_s,
CTR0_o => CTR0_s,
CTR1_o => CTR1_s,
STA_i => STA_s,
DRX0_i => DRX0_s,
DRX1_i => DRX1_s,
DRX2_i => DRX2_s,
DRX3_i => DRX3_s,
DRX4_i => DRX4_s,
DRX5_i => DRX5_s,
DTX0_o => DTX0_s,
DTX1_o => DTX1_s,
DTX2_o => DTX2_s,
DTX3_o => DTX3_s,
load_tx => load_tx_s,
tx_fifo_oen => tx_fifo_oen_s
);
end Behavioral;
hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 12:07:51 10/26/2011
-- Design Name: i2c slave to wb_master testbench
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/rtl/i2c_slave_wb_master/test/i2c_bit_tb.vhd
-- Project Name: CTDAH
-- Target Device: Spartan 6
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_bit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY i2c_bit_tb IS
END i2c_bit_tb;
ARCHITECTURE behavior OF i2c_bit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
component i2c_bit
port(
rst_i : IN std_logic;
wb_clk_i : IN std_logic;
presc_e : IN std_logic;
presc : IN std_logic_vector(15 downto 0);
done : OUT std_logic;
sda_i : IN std_logic;
scl_i : IN std_logic;
start_o : OUT std_logic;
pause_o : OUT std_logic;
rcved_o : OUT std_logic
);
end component;
--Inputs
signal rst_i : std_logic := '0';
signal wb_clk_i : std_logic := '0';
signal presc_e : std_logic := '0';
signal presc : std_logic_vector(15 downto 0) := (others => '0');
signal sda_i : std_logic := '0';
signal scl_i : std_logic := '0';
--Outputs
signal done : std_logic;
signal start_o : std_logic;
signal pause_o : std_logic;
signal rcved_o : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant wb_clk_i_period : time := 50 ns; -- @ 20 MHz
constant scl_i_period : time := 2500 ns; -- @ 400 KHz
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_bit
PORT MAP (
rst_i => rst_i,
wb_clk_i => wb_clk_i,
presc_e => presc_e,
presc => presc,
done => done,
sda_i => sda_i,
scl_i => scl_i,
start_o => start_o,
pause_o => pause_o,
rcved_o => rcved_o
);
-- procedure stop is
-- begin
-- end procedure;
--
-- procedure one is
-- begin
-- end procedure;
--
-- procedure zero is
-- begin
-- end procedure;
-- Clock process definitions
wb_clk_i_process :process
begin
wb_clk_i <= '1';
wait for wb_clk_i_period/2;
wb_clk_i <= '0';
wait for wb_clk_i_period/2;
end process;
scl_i_process :process
begin
scl_i <= '1';
wait for scl_i_period/2;
scl_i <= '0';
wait for scl_i_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure init_cond is
begin
sda_i <= '1';
scl_i <= 'Z';
end init_cond;
procedure rst is
begin
wait for wb_clk_i_period*2;
rst_i <= '1';
wait for wb_clk_i_period*2;
rst_i <= '0';
wait for wb_clk_i_period*2;
end rst;
procedure start is
begin
sda_i <= '1';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '0';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end start;
procedure addr_send(addr : STD_LOGIC_VECTOR(6 downto 0)) is
begin
for i in 0 to 6 loop
sda_i <= addr(i);
wait for scl_i_period;
end loop;
end addr_send;
procedure pause is
begin
sda_i <= '0';
wait until rising_edge(scl_i);
wait for scl_i_period/4;
sda_i <= '1';
wait until falling_edge(scl_i);
wait for scl_i_period/4;
end pause;
begin
init_cond;
rst;
start;
addr_send("0101100");
pause;
-- insert stimulus here
wait;
end process;
END;
hdl/rtl/i2c_slave_wb_master/test/i2c_slave_top_tb.vhd deleted 100755 → 0
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hdl/rtl/i2c_wb_access_ctrl/rtl/i2c_wb_access_ctrl.vhd deleted 100755 → 0
View file @ dcfde77a
----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:50:12 11/25/2011
-- Design Name: i2c_wb_access_ctrl
-- Module Name: i2c_wb_access_ctrl - Behavioral
-- Project Name: i2c to wishbone access controller
-- Target Devices: Spartan 6
-- Tool versions:
-- Description: This is the moduel that controls the access to the wishbone modules
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_wb_access_ctrl is
generic(
g_WISHBONE_MODULES: NATURAL := 4;
g_WISHBONE_MEMWIDTH: NATURAL := 16
);
port (
rst : in STD_LOGIC;
wb_clk : in STD_LOGIC;
wb_stb_o : out STD_LOGIC;
wb_cyc_o : out STD_LOGIC;
wb_sel_o : out STD_LOGIC;
wb_we_o : out STD_LOGIC;
wb_data_i : in STD_LOGIC_VECTOR (31 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (31 downto 0);
wb_addr_o : out STD_LOGIC_VECTOR (3 downto 0);
wb_ack_i : in STD_LOGIC;
wb_rty_i : in STD_LOGIC;
wb_err_i : in STD_LOGIC;
-- Interruptions
ind_wb_addr_i : in STD_LOGIC;
inst_rd_i : in STD_LOGIC;
inst_wr : in STD_LOGIC;
-- Here we add all the wishbone ports needed
wb_cyc_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_sel_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_we_i : in STD_LOGIC_VECTOR (g_WISHBONE_MODULES - 1 downto 0);
wb_data_o : out STD_LOGIC_VECTOR (32*g_WISHBONE_MODULES -1 downto 0);
wb_data_i : in STD_LOGIC_VECTOR (32*g_WISHBONE_MODULES -1 downto 0);
wb_addr_i : in STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_ack_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_rty_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0);
wb_err_o : out STD_LOGIC_VECTOR (g_WISHBONE_MEMWIDTH*g_WISHBONE_MODULES - 1 downto 0)
);
end CTDAH_top;
architecture Behavioral of CTDAH_top is
constant CTDAH_control_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0100"
constant i2c_slave_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0200";
constant trigger_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0300";
constant EEPROM_manager_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0400";
constant wr_core_addr : STD_LOGIC_VECTOR (15 downto 0) := X"0500";
constant EEPROM_memory : STD_LOGIC_VECTOR (15 downto 0) := X"1000";
-------------------------------------------------------------------------------
-- [ 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ]
-- [ RESERVED | X | EN5 | EN4 | EN3 | EN2 | EN1 | EN0 | GEN ]
-------------------------------------------------------------------------------
-- GEN this is the general enable
-- ENi enable access to the given wishbone module
-------------------------------------------------------------------------------
signal CTRL0: STD_LOGIC_VECTOR (15 downto 0);
-------------------------------------------------------------------------------
-- [ 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 ]
-- [ x | x | RD5 | WR5 | RD4 | WR4 | RD3 | WR3 | RD2 | WR2 | RD1 | WR1 | RD0 | WR0 | GRD | GWR ]
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
signal CTRL1: STD_LOGIC_VECTOR (15 downto 0);
begin
process(wb_clk)
variable caseCond0 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(3) & CTR1(2);
variable caseCond1 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(5) & CTR1(4);
variable caseCond2 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(7) & CTR1(6);
variable caseCond3 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(9) & CTR1(8);
variable caseCond4 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(11) & CTR1(10);
variable caseCond5 : STD_LOGIC_VECTOR (1 downto 0) := CTRL1(13) & CTR1(12);
begin
if rising_edge(wb_clk)then
if ind_wb_addr_i = '1' then
-- We do some prefetch depending upon permisssions
case wb_data_o(15 downto 0) is
when CTDAH_control_addr =>
if CTRL0(0) and CTRL0 (1) then
case caseCond0 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when i2c_slave_addr =>
if CTRL0(0) and CTRL0 (2) then
case caseCond1 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when trigger_addr =>
if CTRL0(0) and CTRL0 (3) then
case caseCond2 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when EEPROM_manager_addr =>
if CTRL0(0) and CTRL0 (4) then
case caseCond3 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when wr_core_addr =>
if CTRL0(0) and CTRL0 (5) then
case caseCond4 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when EEPROM_memory =>
if CTRL0(0) and CTRL0 (6) then
case caseCond5 is
when "10"=>
-- Read permissions
when "01"=>
-- Write permissions
when "11"=>
-- Read & write permissions
when others =>
end case;
else
end if;
when others =>
end case;
else
end if;
else
end if;
end process;
end Behavioral;
hdl/rtl/ipcore_dir/RAMID_2048.asy deleted 100755 → 0
View file @ dcfde77a
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 RAMID_2048
RECTANGLE Normal 32 32 544 672
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[10:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[15:0]
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[10:0]
PINATTR Polarity IN
LINE Normal 0 592 32 592
PIN 0 592 LEFT 36
PINATTR PinName rstb
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[15:0]
PINATTR Polarity OUT
hdl/rtl/ipcore_dir/RAMID_2048.gise deleted 100755 → 0
View file @ dcfde77a
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="RAMID_2048.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="RAMID_2048.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="RAMID_2048.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="RAMID_2048.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="RAMID_2048.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/rtl/ipcore_dir/RAMID_2048.ngc deleted 100755 → 0
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This diff is collapsed.
hdl/rtl/ipcore_dir/RAMID_2048.sym deleted 100755 → 0
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="RAMID_2048">
<symboltype>BLOCK</symboltype>
<timestamp>2011-10-16T9:20:59</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[10:0]" />
<pin polarity="Input" x="0" y="112" name="dina[15:0]" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[10:0]" />
<pin polarity="Input" x="0" y="592" name="rstb" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="368" name="doutb[15:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">RAMID_2048</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[10:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[15:0]" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[10:0]" />
<line x2="32" y1="592" y2="592" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="592" type="pin rstb" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[15:0]" />
</graph>
</symbol>
hdl/rtl/ipcore_dir/RAMID_2048.v deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file RAMID_2048.v when simulating
// the core, RAMID_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module RAMID_2048(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [15 : 0] dina;
input clkb;
input rstb;
input [10 : 0] addrb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of RAMID_2048 is "black_box"
endmodule
hdl/rtl/ipcore_dir/RAMID_2048.veo deleted 100755 → 0
View file @ dcfde77a
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
RAMID_2048 YourInstanceName (
.clka(clka),
.wea(wea), // Bus [0 : 0]
.addra(addra), // Bus [10 : 0]
.dina(dina), // Bus [15 : 0]
.clkb(clkb),
.rstb(rstb),
.addrb(addrb), // Bus [10 : 0]
.doutb(doutb)); // Bus [15 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file RAMID_2048.v when simulating
// the core, RAMID_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMID_2048.vhd deleted 100755 → 0
View file @ dcfde77a
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAMID_2048.vhd when simulating
-- the core, RAMID_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY RAMID_2048 IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
END RAMID_2048;
ARCHITECTURE RAMID_2048_a OF RAMID_2048 IS
-- synthesis translate_off
component wrapped_RAMID_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_RAMID_2048 use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_rstb => 1,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAMID_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- synthesis translate_on
END RAMID_2048_a;
hdl/rtl/ipcore_dir/RAMID_2048.vho deleted 100755 → 0
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--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component RAMID_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(15 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(15 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of RAMID_2048: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : RAMID_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file RAMID_2048.vhd when simulating
-- the core, RAMID_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/rtl/ipcore_dir/RAMID_2048.xco deleted 100755 → 0
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##############################################################
#
# Xilinx Core Generator version 12.4
# Date: Sun Oct 16 09:21:46 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx25t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator family Xilinx,_Inc. 4.3
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=RAMID_2048
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Always_Enabled
CSET enable_b=Always_Enabled
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=16
CSET read_width_b=16
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=true
CSET write_depth_a=2048
CSET write_width_a=16
CSET write_width_b=16
# END Parameters
GENERATE
# CRC: cac43165
hdl/rtl/ipcore_dir/RAMID_2048.xise deleted 100755 → 0
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hdl/rtl/ipcore_dir/RAMID_2048_flist.txt deleted 100755 → 0
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# Output products list for <RAMID_2048>
RAMID_2048.asy
RAMID_2048.gise
RAMID_2048.ngc
RAMID_2048.sym
RAMID_2048.v
RAMID_2048.veo
RAMID_2048.vhd
RAMID_2048.vho
RAMID_2048.xco
RAMID_2048.xise
RAMID_2048_flist.txt
RAMID_2048_xmdf.tcl
_xmsgs/pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
hdl/rtl/ipcore_dir/RAMID_2048_xmdf.tcl deleted 100755 → 0
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# The package naming convention is <core_name>_xmdf
package provide RAMID_2048_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::RAMID_2048_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::RAMID_2048_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name RAMID_2048
}
# ::RAMID_2048_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::RAMID_2048_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path RAMID_2048_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module RAMID_2048
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/rtl/ipcore_dir/RAMTT_2048.asy deleted 100755 → 0
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 RAMTT_2048
RECTANGLE Normal 32 32 544 672
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[10:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[127:0]
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[10:0]
PINATTR Polarity IN
LINE Normal 0 592 32 592
PIN 0 592 LEFT 36
PINATTR PinName rstb
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[127:0]
PINATTR Polarity OUT
hdl/rtl/ipcore_dir/RAMTT_2048.gise deleted 100755 → 0
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="RAMTT_2048.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="RAMTT_2048.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="RAMTT_2048.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="RAMTT_2048.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="RAMTT_2048.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="RAMTT_2048">
<symboltype>BLOCK</symboltype>
<timestamp>2011-10-16T9:19:0</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[10:0]" />
<pin polarity="Input" x="0" y="112" name="dina[127:0]" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[10:0]" />
<pin polarity="Input" x="0" y="592" name="rstb" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="368" name="doutb[127:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">RAMTT_2048</text>
<rect width="512" x="32" y="32" height="640" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[10:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[127:0]" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[10:0]" />
<line x2="32" y1="592" y2="592" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="592" type="pin rstb" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[127:0]" />
</graph>
</symbol>
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/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file RAMTT_2048.v when simulating
// the core, RAMTT_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module RAMTT_2048(
clka,
wea,
addra,
dina,
clkb,
rstb,
addrb,
doutb);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [127 : 0] dina;
input clkb;
input rstb;
input [10 : 0] addrb;
output [127 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V4_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(1),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(128),
.C_READ_WIDTH_B(128),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(128),
.C_WRITE_WIDTH_B(128),
.C_XDEVICEFAMILY("spartan6"))
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.RSTB(rstb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of RAMTT_2048 is "black_box"
endmodule
hdl/rtl/ipcore_dir/RAMTT_2048.veo deleted 100755 → 0
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/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
RAMTT_2048 YourInstanceName (
.clka(clka),
.wea(wea), // Bus [0 : 0]
.addra(addra), // Bus [10 : 0]
.dina(dina), // Bus [127 : 0]
.clkb(clkb),
.rstb(rstb),
.addrb(addrb), // Bus [10 : 0]
.doutb(doutb)); // Bus [127 : 0]
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file RAMTT_2048.v when simulating
// the core, RAMTT_2048. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
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--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file RAMTT_2048.vhd when simulating
-- the core, RAMTT_2048. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY RAMTT_2048 IS
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(127 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(127 downto 0));
END RAMTT_2048;
ARCHITECTURE RAMTT_2048_a OF RAMTT_2048 IS
-- synthesis translate_off
component wrapped_RAMTT_2048
port (
clka: in std_logic;
wea: in std_logic_vector(0 downto 0);
addra: in std_logic_vector(10 downto 0);
dina: in std_logic_vector(127 downto 0);
clkb: in std_logic;
rstb: in std_logic;
addrb: in std_logic_vector(10 downto 0);
doutb: out std_logic_vector(127 downto 0));
end component;
-- Configuration specification
for all : wrapped_RAMTT_2048 use entity XilinxCoreLib.blk_mem_gen_v4_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 1,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 128,
c_initb_val => "0",
c_family => "spartan6",
c_read_width_a => 128,
c_disable_warn_bhv_coll => 0,
c_use_softecc => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_softecc_output_regs_b => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan6",
c_write_depth_b => 2048,
c_write_depth_a => 2048,
c_has_rstb => 1,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 11,
c_has_softecc_input_regs_a => 0,
c_addrb_width => 11,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 128,
c_write_width_a => 128,
c_read_depth_b => 2048,
c_read_depth_a => 2048,
c_byte_size => 9,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 1,
c_has_enb => 0,
c_web_width => 1,
c_has_ena => 0,
c_use_byte_web => 0,
c_use_byte_wea => 0,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RAMTT_2048
port map (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb);
-- synthesis translate_on
END RAMTT_2048_a;
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# Output products list for <RAMTT_2048>
RAMTT_2048.asy
RAMTT_2048.gise
RAMTT_2048.ngc
RAMTT_2048.sym
RAMTT_2048.v
RAMTT_2048.veo
RAMTT_2048.vhd
RAMTT_2048.vho
RAMTT_2048.xco
RAMTT_2048.xise
RAMTT_2048_flist.txt
RAMTT_2048_xmdf.tcl
_xmsgs/pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_readme.txt
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/project/ipcore_dir/tmp/_cg/RAMID_2048.vhd&quot; into library work</arg>
</msg>
</messages>
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SET designentry = VHDL
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = spartan6
SET device = xc6slx25t
SET package = csg324
SET speedgrade = -3
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
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