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FMC ADC 100M 14b 4cha - Gateware
Commit 426788b5 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl/sim: sanitized and updated SVEC simulation. Tested with ModelSIM 10.2a, works.

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.gitignore
View file @ 426788b5
hdl/ip_cores/.lso hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs hdl/ip_cores/_xmsgs
hdl/*/sim/transcript hdl/*/sim/*/transcript
hdl/*/sim/vsim.wlf hdl/*/sim/*/vsim.wlf
hdl/*/sim/Makefile hdl/*/sim/*/Makefile
hdl/*/sim/modelsim.ini hdl/*/sim/*/modelsim.ini
hdl/*/sim/work/ hdl/*/sim/*/work/
hdl/*/testbench/top/transcript hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile hdl/*/testbench/top/Makefile
......
hdl/svec/sim/2048Mb_ddr3/ddr3_parameters.vh
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...@@ -559,7 +559,8 @@ ...@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin `else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
......
hdl/svec/sim/testbench/Makefile deleted 100644 → 0
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This diff is collapsed.
hdl/svec/sim/testbench/Manifest.py
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sim_tool="modelsim"
top_module="main"
action = "simulation" action = "simulation"
target = "xilinx" target = "xilinx"
syn_device = "xc6slx150t"
vlog_opt="+incdir+../vme64x_bfm +incdir+../2048Mb_ddr3" include_dirs=["../vme64x_bfm", "../2048Mb_ddr3", "../../../ip_cores/general-cores/sim"]
files = [ "main.sv", files = [ "main.sv",
"../../../ip_cores/adc_sync_fifo.vhd", "../../../ip_cores/adc_sync_fifo.vhd",
...@@ -21,3 +23,5 @@ modules = { "local" : [ "../../rtl", ...@@ -21,3 +23,5 @@ modules = { "local" : [ "../../rtl",
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]} "git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
fetchto="../../../ip_cores" fetchto="../../../ip_cores"
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
hdl/svec/sim/testbench/main.sv
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...@@ -117,7 +117,9 @@ module main; ...@@ -117,7 +117,9 @@ module main;
int i, result; int i, result;
CBusAccessor_VME64x acc = new(VME.master); CBusAccessor_VME64x acc;
acc = new(VME.master);
#20us; #20us;
......
hdl/svec/sim/testbench/svec.do
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vsim -novopt -t 1ps main vsim -novopt -t 1ps main
log -r /* #log -r /*
set StdArithNoWarnings 1 set StdArithNoWarnings 1
set NumericStdNoWarnings 1 set NumericStdNoWarnings 1
#view wave #view wave
#view transcript #view transcript
#do wave_interrupt.do do wave_interrupt.do
do wave_ddr.do #do wave_ddr.do
#do wave.do
radix -hexadecimal radix -hexadecimal
run 50 us run 50 us
......
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