hdl: removed carrier one-wire master (now handled by WR PTP core), introduced…

hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)

hdl: removed carrier one-wire master (now handled by WR PTP core), introduced…
hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)
cff7f492 · Dimitris Lampridis · Dimitris Lampridis · f314bd8a · cff7f492 · cff7f492
Commit cff7f492 authored Jul 05, 2016 by Dimitris Lampridis Committed by Dimitris Lampridis Oct 24, 2018
Expand all Hide whitespace changes
Inline Side-by-side

Showing with 105 additions and 107 deletions

spec_top_fmc_adc_100Ms.vhd hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd +92 -107

spec_top_fmc_adc_100Ms.ucf hdl/spec/spec_top_fmc_adc_100Ms.ucf +13 -0

No files found.
--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
--- a/hdl/spec/spec_top_fmc_adc_100Ms.ucf
+++ b/hdl/spec/spec_top_fmc_adc_100Ms.ucf
@@ -516,6 +516,19 @@ NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
 NET "DDR3_DQ[15]" LOC = Y1;
 NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";

+
+#----------------------------------------
+# SPI FLASH
+#----------------------------------------
+NET "SPI_NCS_O"  LOC = AA3;
+NET "SPI_NCS_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_SCLK_O" LOC = Y20;
+NET "SPI_SCLK_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_MOSI_O" LOC = AB20;
+NET "SPI_MOSI_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_MISO_I" LOC = AA20;
+NET "SPI_MISO_I"  IOSTANDARD = "LVCMOS25";
+
 #----------------------------------------
 # UART
 #----------------------------------------