Serdes pll feedback is now cancelling the clock path delay.
See UG382 Spartan-6 FPGA Clocking Resources page 33.

spec -> feedback through a buffer.
svec -> direct feedback (without buffer).

The timetag core is meant to be shared between different carriers.

The ip_cores dir is meant to be shared between different carriers.

The new module contains another wb crossbar. Therefore the memory
mapping has changed.
This has been done for the future svec design with two fmc slots.

This solves the problem of trigger firing even when the data was below the threshold.