Commits · 6012a665b389f65a10a5a6f2c3fd4c98d3f31202 · Projects / Hdlmake · Open Hardware Repository

31 May, 2019 12 commits
- testsuite: add tests for configparser. · 6012a665
  Tristan Gingold authored May 31, 2019
  
  6012a665
- testsuite: add a test for vhdl_parser. · 751f178c
  Tristan Gingold authored May 31, 2019
  
  751f178c
- testsuite: improve testing of gitsm · 6be11c94
  Tristan Gingold authored May 31, 2019
  
  6be11c94
- Improve python3 compatibility for git/gitsm. · 1a91c34f
  Tristan Gingold authored May 31, 2019
  
  1a91c34f
- Remove unused function from path.py · c1c5a172
  Tristan Gingold authored May 31, 2019
  
  c1c5a172
- testsuite: add tests for verilog parser. · a1c642be
  Tristan Gingold authored May 31, 2019
  
  a1c642be
- testsuite: add a test for xci · 26217857
  Tristan Gingold authored May 31, 2019
  
  26217857
- Remove unused files/functions. · 27ed0109
  Tristan Gingold authored May 31, 2019
  
  27ed0109
- Add a testsuite. · a8ffeb23
  Tristan Gingold authored May 31, 2019
  
  a8ffeb23
- __main__: add a top-level function to support a testsuite. · 7d7aad4b
  Tristan Gingold authored May 31, 2019
  
  7d7aad4b
- Close generated makefile file descriptor. · 81895179
  Tristan Gingold authored May 31, 2019
```
Preliminary work to support a testsuite.
```
  81895179
- Fix crash in manifest-help · 800f3e37
  Tristan Gingold authored May 31, 2019
  
  800f3e37
08 May, 2019 1 commit
- Add parsing of XCI files to locate Vivado IP module names. · f125d15f
  Tristan Gingold authored May 08, 2019
```
From Nick Brereton
```
  f125d15f
11 Apr, 2019 2 commits
- Bump version to 3.2 · c4b5fced
  Javier D. Garcia-Lasheras authored Apr 11, 2019
  
  c4b5fced
- Update docs with the new Quartus property dictionary format · 54db6764
  Javier D. Garcia-Lasheras authored Apr 11, 2019
  
  54db6764
09 Apr, 2019 1 commit
- Fix for issue #35 , improve ifdef matching in Verilog parser · e56bcca8
  Javier D. Garcia-Lasheras authored Apr 09, 2019
  
  e56bcca8
04 Apr, 2019 2 commits
- Provide the Quartus properties as a dictionary · edb220cb
  Javier D. Garcia-Lasheras authored Apr 04, 2019
  
  edb220cb
- Escape quotations in the Quartus Makefile user properties · 63139ec6
  Javier D. Garcia-Lasheras authored Apr 04, 2019
  
  63139ec6
03 Apr, 2019 2 commits
- Do not try to synthesize Verilog and SystemVerilog includes · 71b60dde
  Javier D. Garcia-Lasheras authored Apr 03, 2019
  
  71b60dde
- Do not enable SystemVerilog 2005 in Quartus, but support syn_properties in the Manifest · a348e326
  Javier D. Garcia-Lasheras authored Apr 03, 2019
  
  a348e326
02 Apr, 2019 3 commits
- Enable SystemVerilog 2005 as default Verilog input version in Quartus · 2f5ab537
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  2f5ab537
- Add include_dirs as SEARCH_PATH in Quartus · 49cc92e6
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  49cc92e6
- Fix System Verilog files included on Verilog synthesis list · 6bda472d
  Javier D. Garcia-Lasheras authored Apr 02, 2019
  
  6bda472d
01 Apr, 2019 1 commit
- Hot Fix include_dirs mechanism · ba831ab5
  Javier D. Garcia-Lasheras authored Apr 01, 2019
  
  ba831ab5
30 Mar, 2019 11 commits
- Bump version to 3.1 · ffa3ba6c
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  ffa3ba6c
- Fix typo in Xilinx ISim at the supported tools table in docs · ecef800f
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  ecef800f
- Fix missing makefile command in the prefix and sufix examples · e826f6e1
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  e826f6e1
- Fix and upgrade the counter test demo HDL files · c97cff89
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  c97cff89
- Improve how new_dep_solver handles a missing top_module definition · 1627ac83
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  1627ac83
- Adjust links in the documents to the new GitLab management · b3a15d2d
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  b3a15d2d
- Quit upon error should generate an error code different than 0 · d8233b71
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  d8233b71
- Include a note in the docs about Modelsim +incdir+ management · 4c8d351c
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  4c8d351c
- Test of Active-HDL failes under CMD · 302aab7d
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  302aab7d
- Fix Active-HDL support in Windows Cmd and PowerShell · 2431e387
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  2431e387
- Fix file source handling in Diamond and Libero · 13f5d20e
  Javier D. Garcia-Lasheras authored Mar 30, 2019
  
  13f5d20e
29 Mar, 2019 5 commits
- More helpful error message when no action set causing tool not to be set. · 7959a8de
  William Kamp authored Jul 25, 2018
  
  7959a8de
- Better support multiple VHDL libraries. · 033590e1
  William Kamp authored Jul 25, 2018
```
VHDL_parser.py extracts the library from instantiations.
new_dep_solver.py does not assume the work library.
core.py inherits the library from the parent Manifest.
```
  033590e1
- Fix incl_makefiles being ignored at synthesis and simulation · 26f08930
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  26f08930
- Fix ISIM support for mixed HDL languages · 4043e15b
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  4043e15b
- XCO files should be handled by ISE, not only by Vivado and PlanAhead. · d3824c98
  Javier D. Garcia-Lasheras authored Mar 29, 2019
  
  d3824c98