Major cleanup of VHDL code

Signed-off-by: Tom Levens <tom.levens@cern.ch>

Major cleanup of VHDL code
Signed-off-by: Tom Levens <tom.levens@cern.ch>
af4ec2d0 · Tom Levens · ae18039d · af4ec2d0 · af4ec2d0 · af4ec2d0
Commit af4ec2d0 authored Jan 04, 2017 by Tom Levens
17 changed files
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
--- a/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
+++ b/hdl/vme64x-core/rtl/VME_Access_Decode.vhd
--- a/hdl/vme64x-core/rtl/VME_Am_Match.vhd
+++ b/hdl/vme64x-core/rtl/VME_Am_Match.vhd
--- a/hdl/vme64x-core/rtl/VME_CRAM.vhd
+++ b/hdl/vme64x-core/rtl/VME_CRAM.vhd
--______________________________________________________________________________|
+--------------------------------------------------------------------------------
--                             VME TO WB INTERFACE                              |
+-- CERN (BE-CO-HT)
--                                                                              |
+-- VME64x Core
--                                CERN,BE/CO-HT                                 |
+-- http://www.ohwr.org/projects/vme64x-core
--______________________________________________________________________________|
+--------------------------------------------------------------------------------
-- File:                        VME_CRAM.vhd                                  |
+--
--______________________________________________________________________________|
+-- unit name:     VME_CRAM (VME_CRAM.vhd)
-- Description: RAM memory
+--
--______________________________________________________________________________
+-- author:        Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Authors:                                      
+--                Davide Pedretti       <davide.pedretti@cern.ch>
--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+--
--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+-- description:   RAM memory
-- Date         11/2012                                                                           
+--
-- Version      v0.03  
+-- dependencies:
--______________________________________________________________________________
+--
+--------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
--                              ------------------------------------    
+--------------------------------------------------------------------------------
-- Copyright (c) 2009 - 2011 CERN                           
+-- This source file is free software; you can redistribute it and/or modify it
-- This source file is free software; you can redistribute it and/or modify it under the terms of 
+-- under the terms of the GNU Lesser General Public License as published by the
-- the GNU Lesser General Public License as published by the Free Software Foundation; either     
+-- Free Software Foundation; either version 2.1 of the License, or (at your
-- version 2.1 of the License, or (at your option) any later version.                             
+-- option) any later version. This source is distributed in the hope that it
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.     
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.                                    
+-- See the GNU Lesser General Public License for more details. You should have
-- You should have received a copy of the GNU Lesser General Public License along with this       
+-- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- last changes: see log.
+--------------------------------------------------------------------------------
+-- TODO: -
+--------------------------------------------------------------------------------
+library ieee;
-library IEEE;
+use ieee.std_logic_1164.all;
-use IEEE.STD_LOGIC_1164.ALL;
+use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
 use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
+entity VME_CRAM is
--===========================================================================
+  generic (
- entity VME_CRAM is
+    dl : integer;
- generic (dl : integer; 		
    al : integer := f_log2_size(c_CRAM_SIZE)
  );
- port (clk  : in std_logic; 			
+  port (
+    clk : in  std_logic;
    we  : in  std_logic;
- 	aw    : in std_logic_vector(al - 1 downto 0); 	 
+    aw  : in  std_logic_vector(al-1 downto 0);
- 	di   : in std_logic_vector(dl - 1 downto 0); 
+    di  : in  std_logic_vector(dl-1 downto 0);
- 	dw  : out std_logic_vector(dl - 1 downto 0)
+    dw  : out std_logic_vector(dl-1 downto 0)
  );
- end VME_CRAM; 
+end VME_CRAM;
--===========================================================================
+architecture syn of VME_CRAM is
-- Architecture declaration
--===========================================================================
- architecture syn of VME_CRAM is 
- type ram_type is array (2**al - 1 downto 0) of std_logic_vector (dl - 1 downto 0); 
+  type ram_type is array (2**al-1 downto 0) of std_logic_vector (dl-1 downto 0);
  signal CRAM : ram_type;
--===========================================================================
-- Architecture begin
--===========================================================================
 begin
- process (clk) 
+  process (clk) begin
- begin 
+    if rising_edge(clk) then
- 	if (clk'event and clk = '1') then  
      if (we = '1') then
- 			CRAM(conv_integer(aw)) <= di; 
+        CRAM(to_integer(unsigned(aw))) <= di;
      end if;
-		dw <= CRAM(conv_integer(aw));
+      dw <= CRAM(to_integer(unsigned(aw)));
    end if;
  end process;
- end syn;
+end syn;
--===========================================================================
-- Architecture end
--===========================================================================
--- a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
--- a/hdl/vme64x-core/rtl/VME_CR_pack.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_pack.vhd
--- a/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
+++ b/hdl/vme64x-core/rtl/VME_CSR_pack.vhd
--________________________________________________________________________________________________
+--------------------------------------------------------------------------------
--                             VME TO WB INTERFACE
+-- CERN (BE-CO-HT)
+-- VME64x Core
+-- http://www.ohwr.org/projects/vme64x-core
+--------------------------------------------------------------------------------
 --
--                                CERN,BE/CO-HT 
+-- unit name:     VME_CSR_pack (VME_CSR_pack.vhd)
--________________________________________________________________________________________________
+--
-- File:                         VME_CSR_pack.vhd
+-- author:        Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
--________________________________________________________________________________________________
+--                Davide Pedretti       <davide.pedretti@cern.ch>
-- Description: This file defines the default configuration of the CSR space after power-up or 
+--
-- software reset.
+-- description:   This file defines the default configuration of the CSR space
--______________________________________________________________________________
+--                after power-up or software reset.
-- Authors:                                      
+--
--               Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)                             
+-- dependencies:
--               Davide Pedretti       (Davide.Pedretti@cern.ch)  
+--
-- Date         06/2012                                                                           
+--------------------------------------------------------------------------------
-- Version      v0.02  
--______________________________________________________________________________
 -- GNU LESSER GENERAL PUBLIC LICENSE
--                              ------------------------------------    
+--------------------------------------------------------------------------------
-- Copyright (c) 2009 - 2011 CERN                           
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your option) 
+-- Free Software Foundation; either version 2.1 of the License, or (at your
-- any later version. This source is distributed in the hope that it will be useful, 
+-- option) any later version. This source is distributed in the hope that it
-- but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
+-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for 
+-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- more details. You should have received a copy of the GNU Lesser General Public 
+-- See the GNU Lesser General Public License for more details. You should have
-- License along with this source; if not, download it from 
+-- received a copy of the GNU Lesser General Public License along with this
-- http://www.gnu.org/licenses/lgpl-2.1.html                     
+-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+-- last changes: see log.
-library IEEE;
+--------------------------------------------------------------------------------
-use IEEE.STD_LOGIC_1164.all;
+-- TODO: -
-use IEEE.numeric_std.all;
+--------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use work.vme64x_pack.all;
-package VME_CSR_pack is
-constant c_csr_array : 	t_CSRarray :=
-(
-BAR  => x"00", --CR/CSR BAR
-BIT_SET_CLR_REG  => x"00", --Bit set register -- 0x10=module enable
-USR_BIT_SET_CLR_REG  => x"00", --Bit clear register
-CRAM_OWNER  => x"00", --CRAM_OWNER
-FUNC0_ADER_0 =>x"00",  --A32_S   "24"
-FUNC0_ADER_1 =>x"00",  --        "00"
-FUNC0_ADER_2 =>x"00",  --        "00"
-FUNC0_ADER_3 =>x"00",  --        "c0"
-FUNC1_ADER_0 =>x"00",  --A24_S   "e4"
+package VME_CSR_pack is
-FUNC1_ADER_1 =>x"00",  --        "00"
-FUNC1_ADER_2 =>x"00",  --        "c0" 
-FUNC1_ADER_3 =>x"00",  --        "00"  
-FUNC2_ADER_0 =>x"00",   --A16_S  "a4"
-FUNC2_ADER_1 =>x"00",  --        "c0"
-FUNC2_ADER_2 =>x"00",  --        "00"
-FUNC2_ADER_3 =>x"00",  --        "00"
-FUNC3_ADER_0 =>x"00",   --A64_S  "04"
-FUNC3_ADER_1 =>x"00",
-FUNC3_ADER_2 =>x"00",
-FUNC3_ADER_3 =>x"00",
-FUNC4_ADER_0 =>x"00",   --used for decoding the FUNC3
-FUNC4_ADER_1 =>x"00",   --used for decoding the FUNC3
-FUNC4_ADER_2 =>x"00",   --used for decoding the FUNC3
-FUNC4_ADER_3 =>x"00",   --used for decoding the FUNC3 "c0"
-FUNC5_ADER_0 =>x"00",
-FUNC5_ADER_1 =>x"00",
-FUNC5_ADER_2 =>x"00",
-FUNC5_ADER_3 =>x"00",
-FUNC6_ADER_0 =>x"00",
-FUNC6_ADER_1 =>x"00",
-FUNC6_ADER_2 =>x"00",
-FUNC6_ADER_3 =>x"00",
-IRQ_Vector   =>x"00",  --"00" because each Slot has a different IRQ Vector
+  constant c_csr_array : t_CSRarray := (
+    BAR                 => x"00",  -- CR/CSR BAR
+    BIT_SET_CLR_REG     => x"00",  -- Bit set register
+                                   -- 0x10 = module enable
+    USR_BIT_SET_CLR_REG => x"00",  -- Bit clear register
+    CRAM_OWNER          => x"00",  -- CRAM_OWNER
+    FUNC0_ADER_0        => x"00",  -- A32_S  "24"
+    FUNC0_ADER_1        => x"00",  --        "00"
+    FUNC0_ADER_2        => x"00",  --        "00"
+    FUNC0_ADER_3        => x"00",  --        "c0"
+    FUNC1_ADER_0        => x"00",  -- A24_S  "e4"
+    FUNC1_ADER_1        => x"00",  --        "00"
+    FUNC1_ADER_2        => x"00",  --        "c0"
+    FUNC1_ADER_3        => x"00",  --        "00"
+    FUNC2_ADER_0        => x"00",  -- A16_S  "a4"
+    FUNC2_ADER_1        => x"00",  --        "c0"
+    FUNC2_ADER_2        => x"00",  --        "00"
+    FUNC2_ADER_3        => x"00",  --        "00"
+    FUNC3_ADER_0        => x"00",  -- A64_S  "04"
+    FUNC3_ADER_1        => x"00",
+    FUNC3_ADER_2        => x"00",
+    FUNC3_ADER_3        => x"00",
+    FUNC4_ADER_0        => x"00",  -- used for decoding the FUNC3
+    FUNC4_ADER_1        => x"00",  -- used for decoding the FUNC3
+    FUNC4_ADER_2        => x"00",  -- used for decoding the FUNC3
+    FUNC4_ADER_3        => x"00",  -- used for decoding the FUNC3 "c0"
+    FUNC5_ADER_0        => x"00",
+    FUNC5_ADER_1        => x"00",
+    FUNC5_ADER_2        => x"00",
+    FUNC5_ADER_3        => x"00",
+    FUNC6_ADER_0        => x"00",
+    FUNC6_ADER_1        => x"00",
+    FUNC6_ADER_2        => x"00",
+    FUNC6_ADER_3        => x"00",
+    IRQ_Vector          => x"00",  -- "00" because each Slot has a different IRQ Vector
                                   -- and the VME Master should set this value
-IRQ_level    =>x"02",
+    IRQ_level           => x"02",
-WB32bits     =>x"01",  -- 32 bit WB of default
+    WB32bits            => x"01",  -- 32 bit WB of default
-others => (others => '0'));
+    others              => (others => '0')
-end VME_CSR_pack;                                                                
+  );
+end VME_CSR_pack;
--- a/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
+++ b/hdl/vme64x-core/rtl/VME_Funct_Match.vhd
--- a/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
+++ b/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
--- a/hdl/vme64x-core/rtl/VME_Init.vhd
+++ b/hdl/vme64x-core/rtl/VME_Init.vhd
--- a/hdl/vme64x-core/rtl/VME_SharedComps.vhd
+++ b/hdl/vme64x-core/rtl/VME_SharedComps.vhd
--- a/hdl/vme64x-core/rtl/VME_Wb_master.vhd
+++ b/hdl/vme64x-core/rtl/VME_Wb_master.vhd
--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
--- a/hdl/vme64x-core/rtl/VME_swapper.vhd
+++ b/hdl/vme64x-core/rtl/VME_swapper.vhd
--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
-- 
+-- VME64x Core
 -- http://www.ohwr.org/projects/vme64x-core
 --------------------------------------------------------------------------------
 --
-- unit name: xvme64x_core.vhd
+-- unit name:     xvme64x_core (xvme64x_core.vhd)
--
-- author: 
--
-- date: 11-07-2012
 --
-- version: 1.0
+-- author:        Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
 --
-- description: 
+-- description:   Wrapped VME64x Core
 --
 -- dependencies:
 --
 --------------------------------------------------------------------------------
--  Modifications:
--      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)
--          * fixed typo (address <-> data)
--------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
 --------------------------------------------------------------------------------
 -- This source file is free software; you can redistribute it and/or modify it
@@ -39,8 +31,8 @@
 --------------------------------------------------------------------------------
 library ieee;
-use ieee.STD_LOGIC_1164.all;
+use ieee.std_logic_1164.all;
-use WORK.wishbone_pkg.all;
+use work.wishbone_pkg.all;
 use work.vme64x_pack.all;
 entity xvme64x_core is
@@ -52,6 +44,7 @@ entity xvme64x_core is
  port (
    clk_i   : in std_logic;
    rst_n_i : in std_logic;
    VME_AS_n_i      : in  std_logic;
    VME_RST_n_i     : in  std_logic;
    VME_WRITE_n_i   : in  std_logic;
@@ -126,13 +119,13 @@ architecture wrapper of xvme64x_core is
      VME_ADDR_DIR_o  : out std_logic;
      VME_ADDR_OE_N_o : out std_logic;
      VME_RETRY_OE_o  : out std_logic;
-      DAT_i           : in  std_logic_vector(g_wb_data_width - 1 downto 0);
+      DAT_i           : in  std_logic_vector(g_wb_data_width-1 downto 0);
-      DAT_o           : out std_logic_vector(g_wb_data_width - 1 downto 0);
+      DAT_o           : out std_logic_vector(g_wb_data_width-1 downto 0);
-      ADR_o           : out std_logic_vector(g_wb_addr_width - 1 downto 0);
+      ADR_o           : out std_logic_vector(g_wb_addr_width-1 downto 0);
      CYC_o           : out std_logic;
      ERR_i           : in  std_logic;
      RTY_i           : in  std_logic;
-      SEL_o           : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
+      SEL_o           : out std_logic_vector(f_div8(g_wb_data_width)-1 downto 0);
      STB_o           : out std_logic;
      ACK_i           : in  std_logic;
      WE_o            : out std_logic;
@@ -150,7 +143,8 @@ begin  -- wrapper
    generic map (
      g_adem_a32 => g_adem_a32,
      g_adem_a24 => g_adem_a24,
-      g_clock => g_clock_freq)
+      g_clock => g_clock_freq
+    )
    port map (
      clk_i           => clk_i,
      rst_n_i         => rst_n_i,

--- a/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
-- VME64x core package
+-- VME64x Core
 -- http://www.ohwr.org/projects/vme64x-core
 --------------------------------------------------------------------------------
 --
-- unit name: xvme64x_core_pkg.vhd (xvme64x_core_pkg.vhd)
+-- unit name:     xvme64x_core_pkg (xvme64x_core_pkg.vhd)
 --
+-- author:        Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
 --
--
+-- description:   Package for wrapped VME64x Core
-- date: 05-07-2013
--
-- version: 1.0
--
 --
 -- dependencies:
 --
@@ -34,17 +30,16 @@
 -- TODO: -
 --------------------------------------------------------------------------------
-library IEEE;
+library ieee;
-use IEEE.STD_LOGIC_1164.all;
+use ieee.std_logic_1164.all;
-use IEEE.NUMERIC_STD.all;
+use ieee.numeric_std.all;
-use WORK.wishbone_pkg.all;
+use work.wishbone_pkg.all;
 package xvme64x_core_pkg is
  ------------------------------------------------------------------------------
  -- Types declaration
  ------------------------------------------------------------------------------
  type t_vme64x_in is record
    as_n     : std_logic;
    rst_n    : std_logic;
@@ -131,7 +126,8 @@ package xvme64x_core_pkg is
      g_wb_addr_width   : integer                       := 64;
      g_cram_size       : integer                       := 1024;
      g_window_size_a24 : std_logic_vector(31 downto 0) := x"00080000";
-      g_window_size_a32 : std_logic_vector(31 downto 0) := x"00080000");
+      g_window_size_a32 : std_logic_vector(31 downto 0) := x"00080000"
+    );
    port (
      clk_i     : in    std_logic;
      rst_n_i   : in    std_logic;
@@ -141,7 +137,8 @@ package xvme64x_core_pkg is
      master_o  : out   t_wishbone_master_out;
      master_i  : in    t_wishbone_master_in;
      irq_i     : in    std_logic;
-      irq_ack_o : out   std_logic);
+      irq_ack_o : out   std_logic
+    );
  end component xvme64x_core_structs;
 end xvme64x_core_pkg;