- 03 Dec, 2018 5 commits
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Dimitris Lampridis authored
hdl: bump general-cores, vme64x-core and gn4124-core to latest version in preparation for updating the SPEC and SVEC reference designs
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Dimitris Lampridis authored
Every clock management block in Spartan-6 has 2xDCM and 1xPLL. PLLs are therefore a scarcer resource and should be preserved for user applications whenever possible. In this case, it is very much possible to generate the necessary clocks via DCMs. Furthermore, we expose the unused CLKFX output of one of the DCMs (along with a generic to configure the multiplication/division factors), in case it can be used by the user application.
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Dimitris Lampridis authored
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Dimitris Lampridis authored
This guarantees that the 125MHz ref clock and the 62.5MHz system clock will be phase aligned. (This only affects g_fpga_family = spartan6, when g_use_default_plls = true)
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Grzegorz Daniluk authored
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- 20 Nov, 2018 1 commit
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Grzegorz Daniluk authored
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- 16 Nov, 2018 4 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 15 Nov, 2018 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 29 Oct, 2018 1 commit
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Dimitris Lampridis authored
Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a, later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the fiber. The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source for both clock domains of the rx path. Tested on an SPEC, works.
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- 16 Oct, 2018 19 commits
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Maciej Lipinski authored
for VXS, ch1 for PHY connection was added, so it is possible to switch between two SFP ports (not seamlessly). To use the same platform/board with designs that have only one SFP port connected, CH1 (the second) must have default values to leave it hanging unconnected.
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Maciej Lipinski authored
this is needed for WR-BTrain-VXS release
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Maciej Lipinski authored
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Maciej Lipinski authored
this is to make sure that WRPC does not get lost. It is better if it simply restarts. The switchover between SFPs is not meant to be seamless
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Maciej Lipinski authored
[VXS support/bin] updated WRPC binary with fixes and support for FRAM in VXS (tmp solution, clean version to be added to WRPC SW) - fixed one-wire reading of thermometer ID to create MAC - added reading of FRAM (temporarily instead of FLASH)
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
This goas along with the support of dual multiplexed channel for GPT in Virtex5. If we have two multiplexed SFPs, we need to be able to read the ROM of the currently active.
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Maciej Lipinski authored
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Maciej Lipinski authored
I prepared it based on SPEC's board support, I forgot to update vxs package name
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Maciej Lipinski authored
Note that on VXS switch, the last device (id 2) has address width 8 bits (this is needed to be inputed correctly when asked by chipscope)
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Maciej Lipinski authored
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Maciej Lipinski authored
added ISE project file (*xise) because synthesis of VXS require special configuration, otherwise ISE returns internal error. This special configuration is added XST command line option: " -use_new_parser yes". It can be added by clicking the top hierarhy file (vxs_wr_ref_top.vhd) in the "Design Manager", the right-click on "Synthesis -XST" in "Processes" window, from drop menu chose "Process Properties - Synthesis Options" and then input " -use_new_parser yes" on "Other XST Command Line Options"
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Grzegorz Daniluk authored
This reverts commit b3389d12.
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Grzegorz Daniluk authored
This reverts commit 9810ef9a.
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- 22 Aug, 2018 1 commit
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Grzegorz Daniluk authored
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- 17 Aug, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 06 Aug, 2018 1 commit
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Tomasz Wlostowski authored
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- 30 Jul, 2018 1 commit
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Dimitris Lampridis authored
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- 27 Jul, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 04 Jul, 2018 1 commit
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Tomasz Wlostowski authored
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