This infra-cores repo is a cut from this repository
that contains a cut from general modules developed
in the context of the BPM project.

In this way, we can reset MMCM by software

This will be used manually reset the ADC MMCM
by software, every time a clock change happens.

Now, on asserting LOCKED by MMCM, we synchronize it
to the destination clock domain and waits until
the LOCK signal has stabilized for a few clock
cycles.

In this way we can safely use the mmcm_adc_locked
signal as a reset to downstream logic.

Even though we don't have much CORDIC
iterations to yield a good resolution, it's
good to be able to acquire the phase for
debugging purposes.

This is a more semantic name.

This will use the Sirius Booster DDS tables
which differ from Storage ring slightly.

This synthesis profile changes the DDS frequency
table used in position_calc_core

This fixes #68 github issue

On outputting '1' to trigger, we must
drive the FPGA iobuf to '0', as this means
output to FPGA. The same for outputting '0'
to trigger.

Note that we use the direction pin as data
so as to implement a wired-OR logic.

This is important as some acquisition modes
(e.g., triggered) may leave dirty buffers
along the way. So, we flush all of this
on each new acquisition.

This reverts commit 7789ba36.

This avoids having old parameters set
by a previous acquisition.

Instead of comparing to the byte sized pre/full
packet we should be comparing transmitted words.

This is safer as we could have some "old"
data fro a previous acquisition in the
AXI datamover or AXI interconnect buffers.
This would concatenate with the new data.

The received init/end DDR address are already
in bytes. So, we don't want to shift it again.

Previously we were relying on the calculated
full BTT value to be always '1' at the LSBs,
but there are cases in which this is not true:
1<0000000>. This would be cropped to 0, but
instead we would want the clip to the maximum BTT
value.