- 20 Jun, 2017 2 commits
-
-
Lucas Russo authored
This will use the Sirius Booster DDS tables which differ from Storage ring slightly.
-
Lucas Russo authored
-
- 19 Jun, 2017 5 commits
-
-
Lucas Russo authored
-
Lucas Russo authored
-
Lucas Russo authored
-
Lucas Russo authored
-
Lucas Russo authored
This synthesis profile changes the DDS frequency table used in position_calc_core
-
- 15 Jun, 2017 2 commits
-
-
Lucas Russo authored
-
Lucas Russo authored
-
- 14 Jun, 2017 1 commit
-
-
Lucas Russo authored
This fixes #68 github issue
-
- 13 Jun, 2017 2 commits
-
-
Lucas Russo authored
On outputting '1' to trigger, we must drive the FPGA iobuf to '0', as this means output to FPGA. The same for outputting '0' to trigger. Note that we use the direction pin as data so as to implement a wired-OR logic.
-
Lucas Russo authored
This is important as some acquisition modes (e.g., triggered) may leave dirty buffers along the way. So, we flush all of this on each new acquisition.
-
- 12 Jun, 2017 3 commits
-
-
Lucas Russo authored
This reverts commit 7789ba36.
-
Lucas Russo authored
This avoids having old parameters set by a previous acquisition.
-
Lucas Russo authored
Instead of comparing to the byte sized pre/full packet we should be comparing transmitted words.
-
- 09 Jun, 2017 2 commits
-
-
Lucas Russo authored
-
Lucas Russo authored
This is safer as we could have some "old" data fro a previous acquisition in the AXI datamover or AXI interconnect buffers. This would concatenate with the new data.
-
- 08 Jun, 2017 1 commit
-
-
Lucas Russo authored
The received init/end DDR address are already in bytes. So, we don't want to shift it again.
-
- 07 Jun, 2017 3 commits
-
-
Lucas Russo authored
Previously we were relying on the calculated full BTT value to be always '1' at the LSBs, but there are cases in which this is not true: 1<0000000>. This would be cropped to 0, but instead we would want the clip to the maximum BTT value.
-
Lucas Russo authored
On long running acquisitions, BTT was not reseting to the maximum permitted to the memory region, so only the first pass would succeed.
-
Lucas Russo authored
Previously, we were always setting the BTT as 2^22. If we needed to finish early, we just ended the transaction with TLAST. This posed a problem for long-running acquisition (triggered), in that the AXI datamover would continue to write even after the memory region, because the BTT was set to 2^22. Now, we always set it to the maximum of the memory region.
-
- 06 Jun, 2017 4 commits
-
-
Lucas Russo authored
-
Lucas Russo authored
-
Lucas Russo authored
Previously we were comparing the end address with '=', but in most cases the ddr end address is not multiple of the internal address. So, the comparison would never trigger and never wrapping the counter to the initial address, but to 0. This caused long running acquisitions (e.g., external trigger) to overwrite results of other channels.
-
Lucas Russo authored
Previously, on wrapping the AXI transaction counter we would possibly reissue the transaction 2 times in row, the first one at the end of the current transaction and the second one at the beginning of the next one.
-
- 05 Jun, 2017 1 commit
-
-
Lucas Russo authored
-
- 26 May, 2017 4 commits
-
-
Lucas Russo authored
The module gc_ext_sync_pulse requires the generic g_min_pulse_width to be at least the number of "ns" of one input clock cycle. Otherwise, it may not function properly, loosing input signals.
-
Lucas Russo authored
Previously we had an extra path to decode the current state and output the FSM outputs. This incurred longer long timing paths. Now, we output the FSM outputs before changing the state. This , in effect, exhibits the same behaviour for other modules, but improves timing closure.
-
Lucas Russo authored
-
Lucas Russo authored
In order to use the wired-OR logic of the MLVDS standard, we need to output data only when sending data. If we are in output state we drive the data pin to HI and use the direction pin as data, so we can release the bus when not sending. If we are in input state, we just use the data/ direction pins as usual.
-
- 25 May, 2017 1 commit
-
-
Lucas Russo authored
-
- 17 May, 2017 1 commit
-
-
Lucas Russo authored
This is safe to use with AFCv3 boards and delivers fast boot times.
-
- 10 May, 2017 1 commit
-
-
Lucas Russo authored
This file should be generated by hdlmake tool every synthesis and not hardcoded as it was before.
-
- 27 Apr, 2017 1 commit
-
-
Lucas Russo authored
-
- 26 Apr, 2017 1 commit
-
-
Lucas Russo authored
-
- 19 Apr, 2017 1 commit
-
-
Lucas Russo authored
Now, all bitstreams are generated with: - SPI buswidth of 4 - SPI fall edge = true - 3 MHZ SPI flash configuration - 32-bit support as we use 256Mb SPI flash
-
- 06 Apr, 2017 3 commits
-
-
Lucas Russo authored
-
Lucas Russo authored
-
Lucas Russo authored
-
- 30 Mar, 2017 1 commit
-
-
Lucas Russo authored
IOBUF primitives always have the "input" signal available for further use. This means that even when transmitting signals (buffer is output) the input signal will have a copy of the transmitted pulse. This is principle is not a problem, but we were using this signal to count received events, so we changed this to use this signal only if the buffer direction is set to input.
-