Now, on asserting LOCKED by MMCM, we synchronize it
to the destination clock domain and waits until
the LOCK signal has stabilized for a few clock
cycles.

In this way we can safely use the mmcm_adc_locked
signal as a reset to downstream logic.

Even though we don't have much CORDIC
iterations to yield a good resolution, it's
good to be able to acquire the phase for
debugging purposes.

This is a more semantic name.

This will use the Sirius Booster DDS tables
which differ from Storage ring slightly.

This synthesis profile changes the DDS frequency
table used in position_calc_core

This fixes #68 github issue

On outputting '1' to trigger, we must
drive the FPGA iobuf to '0', as this means
output to FPGA. The same for outputting '0'
to trigger.

Note that we use the direction pin as data
so as to implement a wired-OR logic.

This is important as some acquisition modes
(e.g., triggered) may leave dirty buffers
along the way. So, we flush all of this
on each new acquisition.

This reverts commit 7789ba36.

This avoids having old parameters set
by a previous acquisition.

Instead of comparing to the byte sized pre/full
packet we should be comparing transmitted words.

This is safer as we could have some "old"
data fro a previous acquisition in the
AXI datamover or AXI interconnect buffers.
This would concatenate with the new data.

The received init/end DDR address are already
in bytes. So, we don't want to shift it again.

Previously we were relying on the calculated
full BTT value to be always '1' at the LSBs,
but there are cases in which this is not true:
1<0000000>. This would be cropped to 0, but
instead we would want the clip to the maximum BTT
value.

On long running acquisitions, BTT was not
reseting to the maximum permitted to the
memory region, so only the first pass would
succeed.

Previously, we were always setting the BTT as
2^22. If we needed to finish early, we just ended
the transaction with TLAST.

This posed a problem for long-running acquisition
(triggered), in that the AXI datamover would
continue to write even after the memory region,
because the BTT was set to 2^22.

Now, we always set it to the maximum of the memory
region.

Previously we were comparing the end address
with '=', but in most cases the ddr end address
is not multiple of the internal address. So, the
comparison would never trigger and never wrapping
the counter to the initial address, but to 0.

This caused long running acquisitions (e.g., external
trigger) to overwrite results of other channels.

Previously, on wrapping the AXI transaction
counter we would possibly reissue the transaction
2 times in row, the first one at the end of the
current transaction and the second one at the
beginning of the next one.

The module gc_ext_sync_pulse requires the generic
g_min_pulse_width to be at least the number of "ns"
of one input clock cycle. Otherwise, it may not
function properly, loosing input signals.

Previously we had an extra path to decode the
current state and output the FSM outputs.

This incurred longer long timing paths.
Now, we output the FSM outputs before
changing the state. This , in effect,
exhibits the same behaviour for other
modules, but improves timing closure.