This is good, as if there is a timeout on the PCIe
side for some reason not detected (short reading),
on a next llio initialization, it will be reset.

According to AD9510 datasheet this is not needed on this
register only. So, we removed it here.

It didn't add any value to debug. So, we removed it here.

Sometimes, only 30ms is not enough to si57x to reset
(maybe we are a bit oo fast on waiting). So, we use 300ms
and everything worked again.

We ned to make sure we have incoming clock to
ISLA216P ADCs. Otherwise we can't initialize
it with certainty.

This fixes #118.

(cherry picked from commit d174d495)

The previous function was wrong, as it was
configuring trigger iface and not trigger mux.

Added "_BASE" to name address, for consistency
with existing names.

This is very useful on setting/getting registers in
modules that have multiple channels with the same
register definitions.

This way avoids users needing to know how this
is implemented internally and, obviously, decreases
the chances of error.

We don't need to destroy zactor PIPE sockets,
as CZMQ zactor infrastructure already does this.

RFREQ is a 38-bit number, with the 10 MSB
the integer part and the 28 LSB the fractional
part. So, we need to divide RFEQ by 2^28 prior
to the calculation.

This was causing a segfault when reading the frequency