Also point to new, stable release of DDR3 core (1.0) which also fixes the reset logic

It is more natural to read a zero value from a register during normal operation / after reset. Also avoids the extra logic outside of the wbgen carrier_csr which was needed to accomodate the non-default value of '1'

hdl: prevent FSM from going through the pre-trigger state, if there are no pre-trigger samples to be acquired. Fixes the error in the samples counter register when pre_trigger samples was zero.

Because of a -yet to be fully understood- bug, acquisition produces
corrupted samples when number_of_samples is exactly equal to multi_shot dpram
size. So for now, number_of_samples should be less than multi_shot ram size.

hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results

hdl: update ddr3-sp6-core pointer so that it includes the latest Manifest.py of ddr3-sp6-core without any local variables

syn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC. Xilinx ISE project files could be added on official release commits if necessary

syn: updated Manifest.py for SPEC and SVEC to work with latest hdlmake notation for git revisions (@@) and align them with current git submodules

hdl: Change ddr-sp6-core module to master branch, add custom variable to select ddr copntrollers (requires hdlmake v2.1).