fmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bug

hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead

rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing

rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing

From Tom's dma branch.

- fake timestamp generation option
- fixed timestamp calculation in data_formatting.vhd
Still a test bitstream, not fully functional.