Commits · 961a52fa0f37bc77337880a0b9642b42a46bb86f · Projects / Hdlmake · Open Hardware Repository

29 Jul, 2016 3 commits
- Purge broken functionalities: force_tool is not working · 961a52fa
  Javier D. Garcia-Lasheras authored Jul 29, 2016
```
and provides a Makefile target dependent on the hdlmake tool
```
  961a52fa
- Module is now independent from Altera · 68ab75cb
  Javier D. Garcia-Lasheras authored Jul 29, 2016
  
  68ab75cb
- Module is now independent from simulation · 50f030e3
  Javier D. Garcia-Lasheras authored Jul 29, 2016
  
  50f030e3
28 Jul, 2016 3 commits
- Module is now independent from synthesis · 47c2d853
  Javier D. Garcia-Lasheras authored Jul 28, 2016
  
  47c2d853
- Refactoring milestone: the full module package is ranked 10.0/10.0 by Pylint · 0a176158
  Javier D. Garcia-Lasheras authored Jul 28, 2016
  
  0a176158
- Refactoring: focus on ModuleSimulation.py · 87521299
  Javier D. Garcia-Lasheras authored Jul 28, 2016
  
  87521299
27 Jul, 2016 4 commits
- Refactoring ModuleAltera.py · 31f8fa67
  Javier D. Garcia-Lasheras authored Jul 27, 2016
  
  31f8fa67
- Refactoring Module, focus on ModuleContent · c8692b97
  Javier D. Garcia-Lasheras authored Jul 27, 2016
  
  c8692b97
- More refactoring, removing redundant info from Module · 58884d63
  Javier D. Garcia-Lasheras authored Jul 27, 2016
  
  58884d63
- Just another working refactoring checkpoint · 36571faf
  Javier D. Garcia-Lasheras authored Jul 27, 2016
  
  36571faf
26 Jul, 2016 2 commits
- Just a working refactoring checkpoint · 28f89a9e
  Javier D. Garcia-Lasheras authored Jul 26, 2016
  
  28f89a9e
- On progress refactoring: just a working checkpoint · d175223c
  Javier D. Garcia-Lasheras authored Jul 26, 2016
  
  d175223c
25 Jul, 2016 2 commits
- A little bit of refactoring focused on module core · d8eed83f
  Javier D. Garcia-Lasheras authored Jul 25, 2016
  
  d8eed83f
- Partially improve the Module code: focus on Module.py · f1d7e053
  Javier D. Garcia-Lasheras authored Jul 25, 2016
  
  f1d7e053
24 Jul, 2016 4 commits
- Improve the module_pool.py code by using Pylint analysis · ff83acf6
  Javier D. Garcia-Lasheras authored Jul 24, 2016
  
  ff83acf6
- Move the complete module stuff to a new subpackage folder · 03f109d1
  Javier D. Garcia-Lasheras authored Jul 24, 2016
  
  03f109d1
- is_fetched_recursively is not used in the code: delete · 53aab390
  Javier D. Garcia-Lasheras authored Jul 24, 2016
  
  53aab390
- Group all the module plugins in a single class · f51ac355
  Javier D. Garcia-Lasheras authored Jul 24, 2016
  
  f51ac355
23 Jul, 2016 15 commits
- Start moving the module stuff to a dedicated folder · 30e76327
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  30e76327
- make_list_of_modules method is not used in the code: delete · 8b810c56
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  8b810c56
- A more ordered way to process the Manifest dict using super · 55709f50
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  55709f50
- Move some core Module stuff to a new class and refactor Module constructor · 2ba26cdf
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  2ba26cdf
- Move files and submodule contents to a new class · 18bb0278
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  18bb0278
- Move incl_makefiles stuff from Module to ModuleSynthesis, as it's only used by the synthesis tool · a64d51b9
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  a64d51b9
- Move include_dir stuff at Module to ModuleSimulation · 57c808c2
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  57c808c2
- Fix VHDL test for Quartus, missing module path · 70cd68c0
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  70cd68c0
- Move the altera-related stuff at module.py to a new class · c761ca21
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  c761ca21
- Clean the iverilog tool file: this need a revamp · 28ecb151
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  28ecb151
- Bitfile_target is only used in the unused old iverilog recipe · 15814765
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  15814765
- Move the simulation-related stuff at module.py to a new class · 0df84159
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  0df84159
- Move the synthesis-related stuff at module.py to a new class · e76af3da
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  e76af3da
- A more structured Module class · 1896e976
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  1896e976
- Refactor Manifest.py parse & process · bfab4a4e
  Javier D. Garcia-Lasheras authored Jul 23, 2016
  
  bfab4a4e
22 Jul, 2016 3 commits
- Disable the fetch --update option · 65b24a72
  Javier D. Garcia-Lasheras authored Jul 22, 2016
  
  65b24a72
- The flatten option for fetch action is not longer required: this is the default behavior now · f7aee235
  Javier D. Garcia-Lasheras authored Jul 22, 2016
  
  f7aee235
- Add sim_top variable to complement syn_top: top_module is redundant now · 5aa91926
  Javier D. Garcia-Lasheras authored Jul 22, 2016
  
  5aa91926
20 Jul, 2016 1 commit
- Temporarly disable Git submodule recursive fetching · cd77102d
  Javier D. Garcia-Lasheras authored Jul 20, 2016
  
  cd77102d
19 Jul, 2016 2 commits
- A little more of comments about Modules and Pool · dbf8fd2d
  Javier D. Garcia-Lasheras authored Jul 19, 2016
  
  dbf8fd2d
- Get_dep_level detects potential loop issues in designs that are OK: demote the… · 7f95af72
  Javier D. Garcia-Lasheras authored Jul 19, 2016
```
Get_dep_level detects potential loop issues in designs that are OK: demote the critical exception to a warning log message per offending file
```
  7f95af72
16 Jul, 2016 1 commit
- Change the way the module_pool environment is set for a cleaner main process · 695b031e
  Javier D. Garcia-Lasheras authored Jul 16, 2016
  
  695b031e