Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Previously on Altera, there was a non-deterministic delay between
transmission from clk_ref to clk_tx. This came from a FIFO in the
GXB and also that clk_tx was not compensated against clk_ref.

Using deterministic mode with PFD feedback achieves determinism.
There is only a single register instead of the FIFO and the parallel
TX clock is phase matched to the CMU reference clock.

Unfortunately, deterministic mode does not have access to force_dispval.
This necessitates using an 8b10b in the FPGA fabric.

Another change is that the CDR clock is trained by a GXB reference
clock pin for better jitter performance. It is forbidden to cascade
two PLLs in low bandwidth mode. This way the recovered clock can use
low bandwidth as it is never derived from clk_ref (also low bandwidth).

Another change is the reset logic has been rewired. Before the WRC
could reset the GXB and thus kill the RX clock. This led to bad
undefined states in the RX state machiens. Now reset as in the manual.

This was a (faulty) prototype card produced in limited number.
It will be replaced by an entirely new design using Arria5.

This project completely out-of-date compared to the other GSI tops.
When the new card is built, we will just make a completely new top.

After transmitting a frame in software, the LM32 reads out the
timestamp set by hardware. Naturally, this comes after the frame
has been sent, so the LM32 must wait.

Prior to this patch the only thing it could wait for was DMA idle.
However, DMA of the packet completes before the timestamp is ready.
Thus there was a race condition where the LM32 would see an old TS.

Conflicts:
	modules/wr_tlu/wb_timestamp_latch.vhd

Previously on Altera, we used a generic to preload the firmware for WR.
This patch removes this as we can now preload with mif which compiles in
seconds instead of hours (quartus does not handle large generics well).

ISE doesn't support type definitions in expressions.
It doesn't like aliases of variables either.

Many of our platforms have an optional WhiteRabbit addon board.
The Wishbone bus should continue to operate in this case.
Thus the system clock is derived from the local oscillator, and
the white rabbit reference clock is an independent PLL.