adding difault value of new scb_top_bare.vhd input so that all the old stuff works fine (e.g. simulation)

Vivado couldn't place them in previously specified bank.

Vivado couldn't decide which standard to use.

No changes actually

Just to try implementation....

Pinout is random.
No timing exeptions.

The delay resolution has changed.

Fixed data rate in the transceivers IP core  (1 Gb -> 1.25 Gb)
Disabled RX buffer

Should simplify comparison.

Vivado doesn't accept them.