It turned out that WRS-FL uses periph_id 0x7 for v1.0 and
0x6 for v1.5. Updated accordingly.

Apparently, this is helpful for WRS-FL v1.5. Explanation from Hongming:

From: hongming
Sent: 30 November 2023 01:24
To: Maciej Marek Lipinski
Subject: 回复： Re:WRS-FL integration into next WRS firmware release

hi maciej

> we do not fully see/understand how changing g_reverse_dmtd to false
> could help in the problem you described. We need to discuss this change
> (which is quite serious) before proceeding

As you may see, we've changed the VCXO of helper PLL in new HW.
There are two search direction for PLL, corresponding to two frequency
relation between help clock and main/ext clock.
As far as I remember, if the frequency of help clock is higher than
main/ext clock, it should use help clock sampling main/ext clock, while
if if the frequency of help clock is lower than main/ext clock, it should
do the opposite.
In our actual test, the actual frequency of VCXO may be slower than the
claimed frequency. The help VCXO cannot reach the supposed value if we
require the frequency of help clock to be higher than main/ext clock.
What we observed it that in previous settings, the dac output of help
clock reaches to be 64000+ when the dac output of main clock is 30000.
After changing the g_reverse_dmtd and searching direction of help PLL,
the dac output of help clock reaches to be 16500+ when the dac output
of main clock is 30000.

When we look at the hardware implementation to find out the reason, we
have the following information:
- We choose VCXO with a pull range of +-100ppm, without considerating
  the frequency statbility, making the actual APR to be only +-45ppm.
- What's worse is that the Supply Voltage of VCXO is 3.3V and our DAC's
  maximun output is 2.5V.
In current WR implementation, N=16384, which means that we need a VCXO
with APR of 61ppm.

Manifest:
- Before syn: add execution of script to generate files with repo versions
- After syn: add generation of bin file

YML:
- synthesize 8 ports always
- synthesize 18 ports when called manually
- simulate when called manually

- change signal names to more meaningful
  lj_detected_o / lj_present_o to lj_ext_gm_pll_pres_o / lj_ext_gm_clk_diff_o
  lj_rev_id_i to lj_periph_id_i
- added pull-ups to lj_periph_id_i to make sure its "111" when unused
- made the selection of LJ-related peripheral more generic

The Low-Jitter functionality is now integrated on some versions of the
main board of the WRS. As such, we need to detect the LJ functionality
itself, not a board with it. Renamed from LJD to LJ for clarity.

- updated the pin names to reflect the true functionality
- connect only the pin that is used, this is a HACK and will need to be
  changed in the future.

- dac_sel allows to support AD5683R additonally to AD5662 used so far
- other modificatins, mostly clean-ups
  * change pll_status_i to clk_ext_i
  * removed unused constraints

Update scb_top_sim.vhd. given to the unused input ljd signals, '0' value for the simulator to not complain

Update scb_top_sim.vhd so as to add missing and non-used port signals in order simulator doesn't complain

Hm proposed master

See merge request !1

  1. add pll_status_i clock period constraints
  2. correct the TNM_NET name of rx_rec_clk_bufin.

rather than differential signal for 10M input.

    There are three types of wrs: normal wrs(mark as wrs), wrs with LJD
(mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ).
    lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ.
    lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD.
        lj_osc_freq_i=111 means WRSLJ.
        lj_osc_freq_i=others means WRS-LJD.

    lj_osc_freq_i[2 downto 0] need to be pulled up.