This fixes then issue of locking ADN4604
reprogramming after the FPGA has booted, as the
update_n pin is grounded and no one can update the
ADN chip.

This fixes #59 github issue.

This checking is not really necessary and increases
timing

This modification should not needed to be done.
We need a BPM module that we can customize it
according to our needs, but not add/remove modules
for different top designs.

This was causing a "unresolved black-block"
error, as we had another .vhd file with the same
name not bounded to anything.

This enhances the project robustness, as the tcl
file is much easier to version than the XML .xpr
one

Now we can select which LEDs output
we want to have a ORed heartbeat between
the GPIO modules and the heartbeat module.

This reverts commit 8c69f3bf.

For fast acquisition paths (e.g., ADC, ADCSWAP), this would cause
error on long-running acquisitions (i.e., hw or sw trigger).
This is probably related to the fact that the DDR end address
might not be correctly configured after a reset. We must properly
understand the issue (FIXME).

This is just to add more safety to the design,
including properly resetting the registers and
wrapping the DDR address if something terrible
happens.

This is needed because we can abort an acquisition
in the middle of a transaction, causing the AXI
datamover to be in an inconsistent state.

This fixes #57 github issue.

This modules should have been assinged to
ADC clock and not to sys_clk, as the LED is
synchronized with the ADC clk.

In this way, we can send any clock/trigger to FMC
trigger output.

This is the same behavior LED1 used to have on commit
75072245, but now we shifted it to LED2.

This is a precaution measure against unwanted signals
on trig_hw_o when tristate buffer is set to output, which
does not make sense on most cases.

Now, we can control the output direction pin polarity
based on the register field "reg_pol"

This is necessary in cases where the polarity
of the internal FPGA tristate buffers means
different things than the external FPGA tristate
buffers, such as for the AFCv3 SN74AVC1T45 buffers.

This is useful for debugging if the trigger
from a backplane is being acquired correctly.

The module uses 9 bits with BYTE addressing. So we need
at lest 0x1FF addressing mask. For precaution, increase
trigger_mux addressing.

Conflicts:
	hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd