Made links from HDL source files to HDL designer directories to permit
HDL designer to work but make is easy to build firmware if HDL designer not
present

Added some more scripts.

Adding files to build scripts

* Edited top_extphy to include IPBus interface to TPx3 interface.

* Set top module by hand.

* Changed UCF to be hacked-for-telescope version

* Removed unnessary files that were being added to project

* Added clock_sim.vhd , eth_mac_sim.vhd. The "generate" statement will stop them being synthesized but they still need to be in project to avoid errors.

  Added a common delay to all pulses ( needs changing ). Edited triggerlogic to accomodate this.

* Moved s_reset_timestamp_ipbus<='0' , might have been causing a bug in reset

* Edited TPix3_iface to allow the shutter and T0 to be set under IPBus control

* logic_clocks now chooses between external ( from 2-pole Lemo ) and internal ( from sysclk xtal ) clock using a generate statement and generic.

* DUTInterfaces - stretch output trigger pulse to two clock cycles.

Synchronous mode output to TORCH readout.

Input from pc048a clock/sync fanout - clock , T0 , shutter.

 

Wrote simple firmware to exercise DUT interface pins. Puts out a series of pulses on each pin. See https://elog.phy.bris.ac.uk/elog/AIDA/17 as an example

Wrote a pattern generator function that puts out 0101 pattern then a string of 0. Different number of 01 on different bits