Commits · 4db629ed018e3796834044803a438bb0a52250f2 · Projects / FMC TDC 1ns 5cha

07 Aug, 2018 1 commit
- Merge remote-tracking branch 'origin/tom-fifo-readout' into proposed_master · 4db629ed
  Dimitris Lampridis authored Aug 07, 2018
  
  4db629ed
27 Jul, 2018 1 commit
- hdl: minor cleanup or root manifest · e8245b04
  Dimitris Lampridis authored Jul 27, 2018
  
  e8245b04
20 Jul, 2018 1 commit
- hdl: eliminate WB int, bring all submodules up-to-date · 8a82e727
  Dimitris Lampridis authored Jul 20, 2018
  
  8a82e727
19 Dec, 2017 2 commits
- Merge branch 'greg-wrpc-v4.2' · b10c63a4
  Grzegorz Daniluk authored Dec 19, 2017
  
  b10c63a4
- update xilinx project files for SPEC and SVEC · c8b144e8
  Grzegorz Daniluk authored Dec 19, 2017
  
  c8b144e8
18 Dec, 2017 2 commits
- update submodules to use WRPC v4.2 release · 04550a4d
  Grzegorz Daniluk authored Dec 18, 2017
  
  04550a4d
- svec: use the latest v2.0 vme64x-core release · d6596ec5
  Grzegorz Daniluk authored Dec 18, 2017
  
  d6596ec5
11 Dec, 2017 18 commits
- top/spec: disconnect WRPC from FMC EEPROM, now we use Flash · 0109fa2b
  Grzegorz Daniluk authored Dec 11, 2017
  
  0109fa2b
- top/spec: cleanup indentation, remove unused signals · fb772c1d
  Grzegorz Daniluk authored Dec 11, 2017
  
  fb772c1d
- top/spec: reorganized to use WRPC Board wrapper · 02083afa
  Grzegorz Daniluk authored Dec 11, 2017
  
  02083afa
- top/svec: bool2int function is now in general_cores · 3a1b7327
  Grzegorz Daniluk authored Dec 08, 2017
  
  3a1b7327
- top/svec: disconnect WRPC from FMC EEPROM, now we use Flash · 4f827cec
  Grzegorz Daniluk authored Dec 08, 2017
  
  4f827cec
- top/svec: cleanup indentation and remove unused signals · 4c7d3f56
  Grzegorz Daniluk authored Dec 08, 2017
  
  4c7d3f56
- top/svec: reorganized to use WRPC Board wrapper · 6185eb76
  Grzegorz Daniluk authored Dec 08, 2017
  
  6185eb76
- update wr-cores · e665f6c1
  Grzegorz Daniluk authored Dec 08, 2017
  
  e665f6c1
- top/spec: cleanup, ports rename · 48f0a742
  Grzegorz Daniluk authored Dec 08, 2017
  
  48f0a742
- adding etherbone submodule (needed for WR board wrapper) · 98bb71d9
  Grzegorz Daniluk authored Dec 06, 2017
  
  98bb71d9
- update vme64x-core to the latest one by Tristan · 86a9d895
  Grzegorz Daniluk authored Dec 05, 2017
  
  86a9d895
- svec: vme ports to lower case · 5ee897b8
  Grzegorz Daniluk authored Dec 05, 2017
  
  5ee897b8
- update general-cores to match wr-cores v4.2rc · 269cc7d1
  Grzegorz Daniluk authored Dec 04, 2017
  
  269cc7d1
- update wr-cores to the latest proposed_master · 52395a8e
  Grzegorz Daniluk authored Dec 04, 2017
  
  52395a8e
- svec: output 1-PPS to LEMO · e49fb3dc
  Grzegorz Daniluk authored Dec 04, 2017
  
  e49fb3dc
- svec_tdc: add SPI Flash and 1-PPS out signals · 6b5e46a8
  Grzegorz Daniluk authored Nov 27, 2017
  
  6b5e46a8
- Uploaded v7.0 sources with wrpc v 4.1 · 572973e6
  Tomasz Wlostowski authored Nov 24, 2017
  
  572973e6
- fmc_tdc_core: decrease timestamp FIFO size to 512 (so that it fits in the SPEC with WPRC v4.1) · d4e10faf
  Tomasz Wlostowski authored Nov 24, 2017
  
  d4e10faf
08 Mar, 2017 1 commit
- update wrc.ram for spec to fix DAC range problem on some SPECs · b2433b14
  Grzegorz Daniluk authored Mar 08, 2017
  
  b2433b14
17 Jan, 2017 4 commits
- include WRPC LM32 firmware v2.1 for SVEC · 7b2bad61
  Evangelia Gousiou authored Jan 17, 2017
  
  7b2bad61
- include WRPC LM32 firmware v2.1 · 8597e333
  Grzegorz Daniluk authored Jan 17, 2017
  
  8597e333
- adding Xilinx ISE project file for SPEC · 4d681a60
  Grzegorz Daniluk authored Jan 17, 2017
  
  4d681a60
- update gennum core version · 1170651f
  Grzegorz Daniluk authored Jan 17, 2017
  
  1170651f
22 May, 2015 1 commit
- top: updated synthesis descriptors · 3b60a1ec
  Tomasz Wlostowski authored May 22, 2015
  
  3b60a1ec
19 May, 2015 1 commit
- hdl: SPEC top level with refurbished TDC core · 5765c94d
  Tomasz Wlostowski authored May 19, 2015
  
  5765c94d
18 May, 2015 1 commit
- top/spec: removed non-WR top level · caaf87ad
  Tomasz Wlostowski authored May 18, 2015
  
  caaf87ad
12 May, 2015 1 commit
- fmc_tdc_mezzanine: forgot to re-connect direct timestamp output after implementing FIFO readout · 0d812061
  Tomasz Wlostowski authored May 12, 2015
  
  0d812061
29 Apr, 2015 1 commit
- hdl: independent FIFO buffers per channel - top level verified on the SVEC · c2a10e64
  Tomasz Wlostowski authored Apr 29, 2015
  
  c2a10e64
14 Apr, 2015 1 commit
- first version with per-channel FIFOs instead of a shared circular buffer · 8b800231
  Tomasz Wlostowski authored Apr 14, 2015
  
  8b800231
10 Apr, 2015 3 commits
- fmc_tdc_wrapper: squeezed direct readout into 64kB address range · 4e08d33b
  Tomasz Wlostowski authored Apr 10, 2015
  
  4e08d33b
- hdl/syn/svec: added missing Manifest file · 8600d4e2
  Tomasz Wlostowski authored Apr 10, 2015
  
  8600d4e2
- hdl: use proposed_master of general-cores · 5ae41634
  Tomasz Wlostowski authored Apr 10, 2015
  
  5ae41634
09 Apr, 2015 1 commit

Tomasz Wlostowski authored Apr 09, 2015

- squeezed A24 address range to 0.5 MB (to fit a full 24-slot VME crate with TDCs)
- fixed IRQ line synchronization issue

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