- 03 Dec, 2015 1 commit
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Evangelia Gousiou authored
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- 10 Nov, 2015 4 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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- 21 Oct, 2015 2 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
-fmc_masterfip_csr.vhd: macrocyc, turnar and silen counters are 31bits not 32
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- 16 Oct, 2015 1 commit
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Evangelia Gousiou authored
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- 15 Oct, 2015 2 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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- 13 Oct, 2015 1 commit
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Evangelia Gousiou authored
- added fd_txena signal to WRNC csr - cleanup
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- 08 Oct, 2015 3 commits
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Tomasz Wlostowski authored
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Evangelia Gousiou authored
-updated masterfip core: up to 263 frame bytes, corrected core reset, added ext_sync and adc supply signals, ucf. -updated testbench
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Tomasz Wlostowski authored
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- 06 Oct, 2015 1 commit
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Tomasz Wlostowski authored
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- 01 Sep, 2015 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 27 Jul, 2015 1 commit
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Tomasz Wlostowski authored
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- 24 Jul, 2015 1 commit
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Evangelia Gousiou authored
small changes on signals names of fmc_masterfip_csr
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- 22 Jul, 2015 1 commit
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Evangelia Gousiou authored
also small correction on the rx_regs
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- 21 Jul, 2015 1 commit
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Evangelia Gousiou authored
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- 20 Jul, 2015 4 commits
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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Evangelia Gousiou authored
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- 17 Jul, 2015 1 commit
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Evangelia Gousiou authored
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- 14 Jul, 2015 1 commit
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Evangelia Gousiou authored
new architecture of masterfip; only the ser/des in vhdl and then the WRNC will do all the logic; in this commit there is no WRNC, it is a test design for the ser/des.
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- 31 Jul, 2014 1 commit
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unknown authored
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