HDL: jtag pins are now in 'Z' when IDLE. Pull down specified for TDI, TMS in constraint. FIX in the TCL for building the project

Set the JTAG pins in the top level design to be 'Z' so as to program the RT-SB without unpluging the fmc-nanonip. Tested in V2 SB but needs to be done in a more elegant way

Remove the define_clock from Synplufy_Constraint.sdc since it is declared also in the other sdc file. Added build_nanofip.tcl script to automate the build of the project

- synthesis with Synplify Premier (DFF triplication with the tmr attribute; RAM triplication "manually" on the code)

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comments mainly; wf_reset_unit: added s_rstin_c_is_full, s_var_rst_c_is_full as additional way to reset FSMs

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JTAG_contoller: added a counter for the bits that are being played to avoid complicated combinatorial calculations

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also changes on engine control (added state rst_rx) and status_bytes_gen (CRC_wrong check done only for RP_DAT frames)

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- engine control state "produce" finishes upon FES transmission (bf it was before CRC and FES transmission)
- cosmetixx

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no manch. code violations checked finally! we believe that the crc will show errors that may have occurred because of manch.encoding.
corrections in detecting errors if bits are not multiple of 8.



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+esthetix in all

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top level nanofip comments on structure updated

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aesthetics: trailing whitespaces deleted from all the units

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