- 09 Feb, 2024 1 commit
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Shareef Jalloq authored
This commit updates urv_regmem to hardwire x0 to return zero. The previous implementation allowed x0 to be written. The bug was caught using the Riscof architecture test suite which specifically checks for this by writing a value to x0 during at least one of the tests.
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- 01 Nov, 2022 4 commits
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Tristan Gingold authored
Release v1.1 See merge request be-cem-edl/common/urv-core!1
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 11 Oct, 2022 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 15 Sep, 2022 7 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 14 Sep, 2022 4 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 13 Sep, 2022 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 12 Sep, 2022 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 29 Jun, 2022 1 commit
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Tristan Gingold authored
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- 13 Dec, 2021 1 commit
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Tristan Gingold authored
This signal is active when an instruction is read from memory. This also indicates when the bus is not used (and therefore could be used by a scrubber)
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- 29 Nov, 2021 1 commit
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Tristan Gingold authored
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- 26 Feb, 2020 1 commit
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Tristan Gingold authored
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- 12 Feb, 2020 1 commit
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Tristan Gingold authored
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- 11 Feb, 2020 3 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 20 Mar, 2019 4 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 19 Mar, 2019 4 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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