platform/altera: update Arria5 PHY with newer version, add default WR PLLs and introduce Altera WR platform wrapper

- Use the built-in 8b10b encoding/decoding provided by the Altera arria5_phy megafunction. This removes the need for
  the custom encoders/decoders, most of the processes at the end of the top-level vhd file, as well as the need for
  the tx_clk_i port and the two generics.

- Repurpose drop_link_i to reset the two megafunctions (arria5_phy_reconf and arria5_phy).

- Removed the Altera clock controllers. The system works fine without them and they only add skew to the clocks.

- Add tx_clk_o port so that we can pass the tx clock to the phy_ref_clk_i of WR PTP core.

- Introduce 8- and 16-bit PCS variants

- Introduce default PLLs for WR:
  * 1x DMTD PLL:  20MHz clock input, 62.5MHz clock output
  * 1x SYS  PLL: 125MHz clock input, 125MHz, 62.5MHz clock outputs
  * 1x EXT  PLL:  10MHz clock input, 125MHz clock output

- Reset all blocks properly and make sure that phy_ready is syncrhonised to phy_rx_clk

wrc.bram compiled from commit (wrpc-sw repo):
61dfdc2 wrpc sim: missing pl_cnt assignment

for details how it works now.

Short description of changes
- frames are generated in two places: LM32 and main.sv
- frames from LM32 are looped back in main.sv
- frames from main.sv go through WRPC and are looped back by wrf_loopback
- frames generated by main.sv have randome size, Inter-frame gap
  is randome for one bunch of sent frames, and fixed low for stress
  in another bunch of sent frames.
- frames from LM32 are sent as fast as possible, which is sloooow
- frames from LM32 have codes to indicate to the simulation problems
  of reception of previous frame (no other easy way for information
  to pass from LM32 to main.sv
- all frames have seqID which is verified in main.sv
- warnings are thrown when
  * wrong seqID is detected by main.sv
  * when ERROR code is sent by LM32, can be on seqID mismatch, or
    rx function error

NOTE: the software for LM32 is now compiled by proper make config
in wrpc-sw (see wrpc-sw/config): wrpc_sim_defconfig

the script

NOTE: you need to run make before do run.do ...

- in the Endpoint of WRPC, the autonegotiation is enabled
- in the Endpoint of simulation, the autonegotiation was disabled
- This mismatch of configuration prevented stuff from working. Fixed
  by enabling autonegotiation in simulation

- the connection of rx/tx to PHY was wrong, there was (very likely
  unintentional) a loop between tx and rx of PHY.
- since there is the (intentional) loop between sink and source of
  wrpc, frames sent by WRPC SW (LM32) were looping endlessly.

- align code
- remove commented stuff
- make some basic comments

By default, the bit is zero (masked), which means that PPS signal output is masked
when the link status is not ok. This is useful to pervent spurious PPS when in GM
or SLAVE mode and the link goes down.

When the bit is set, then a PPS is always generated (as long as the PPS valid bit
in the ESCR register is set). This is useful in free-running master mode.

Signed-off-by: Adam Wujek <adam.wujek@cern.ch>

Compiled from wrpc-sw:
1c028e8e Merge branch 'minic_fifo' into proposed_master

This also removes Xilinx ISE synthesis warnings like:
wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2>
remains a black-box since it has no binding entity.

Signed-off-by: Adam Wujek <adam.wujek@cern.ch>