Conflicts:

	modules/wr_endpoint/endpoint_vectorized_top.vhd
	modules/wr_endpoint/ep_rx_path.vhd
	modules/wr_endpoint/ep_tx_path.vhd

improved test inj_gen mode configuration (can be changed separately from other config - different valid bit). This was convenient for software control implementation

corrected generation as it was sending 2 bytes more than in the set template (2-byte junk at the end)

corrected test-frame generation using pck_injection (dev/null before VLAN unit cause VLAN unit and injection unit use the same RAM)

bugfix: hanged when dreq=low from PCS at the last word (EOF from CRC) -> one of reaons: ugly bug in pack_fifo_content function

added abort of RTU request - in case of error in the input frame, receiving of frame is aborted, error status sent to SWcore, and the RTU request needs to be aborted as well, otherwise SWcore gets lost

bugfix: when frame corrupted in the header (or vlan unit droping frame cause frame is tagged and port is set to be access) the request to RTU was sent anyway... swcore was dropping frame, then receiving wrong RTU response... a mess. Now no rtu-req is done when frame corrupted in the header. still need to fix swcore->input block

changed the size of tx pcs fifo to an original (master, 20) - I stupiditly done it so big (40) that small frames would not get through

changed the order of modules so that rtu_request is done before rx_buffer (and at the same time as VLANs are handled)

bypass fifo included directly into the CRC module to optimize for speed (2 cycles now) and resources (can use standard fifo)

reverted one optimization (did not work for tagging) and made another optimization - starts passing the data at the last cycle of INSERT_TAG - saved cycle

set generic of rx_wb_master g_cyc_on_stall to TRUE in order to save some cycles at the datat transfer

hack-fix of tx_pcs FIFO - it was >hiding< frames somehow causing the latency for frames with even size to increase from <3 to ~18us - the temporary solution is to use v6_hwfifo which takes more resources

added loads of stuff to debug (with chipcscope) endpoint in the switch - the commit potentially to remove when cleaning

handling of situation when SOF and EOF are in the same cycle -- it prevented RTU request from being made and SWcore to go nuts