# Conflicts:
#	modules/wr_endpoint/ep_timestamping_unit.vhd

updated PCIe Memory map to fit WRPC-v5

added processing system io


updated general cores for axi_wb fix

changed pci_rst_n to perst_n, linked to wrc.bin

linked to wrc.bin

linked to wrc.bin

corrected .bram file

corrected .bram file

corrected .bram file

moved axi related files to general-cores (branch: pascal-axi)

Fixed some bugs

updated general cores with right manifest

Updated tcl, added wrapper

WRITE design clk_10m_p/n_i input is ibufds plus add XDC property for non-clock capable pins.

Adding pll_wr_mode[1:0] for SPEC7 V2

added BMM_INFO_DESIGN property to XDC

Add prsnt_m2c_l_i input pin. Prevents prsnt_m2c_l line to be influenced by a non driven FPGA pin after configuration done.
(it did break the JTAG chain after configuration.

upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd

add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout)
wrc_phy16_direct_dmtd.bram build with:
wrpc-sw.git peter_direct_dmtd SHA 50f1c0e
ppsi.git peter_direct_dmtd SHA bf5f6de

- Add generic parameter for the SDB info of the auxiliary interface of the WRPC.
- Export pps_csync and pps_valid ports from the WRPC.

wr_nic_wrapper: Fix copyright issues.

Fix a place & route error related to the OBUF used for PPS output signal.

It's used only locally in dmtd sampler. We don't have enough global
clock nets in Virtex6 for 18-port version of WRS.