- 25 Jan, 2012 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 24 Jan, 2012 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 23 Jan, 2012 4 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 22 Jan, 2012 9 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 20 Jan, 2012 1 commit
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Maciej Lipinski authored
swcore: added xswc_input block (pWB), debugging stuff, there are bugs in xswc_output (missing some words when stab/stall strange combinations
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- 19 Jan, 2012 2 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 18 Jan, 2012 5 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
swcore[v2->v3 port]: a simple simulation for the wishbonized and wrapped (multiple times) swcore is working ... : sending/receiving few frames
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Maciej Lipinski authored
swcore[v2->v3 port] wrappers for the wishbonized (xswc_core) swcore written, they enable the pWB emulators to talk to xswc_core (two wrappers needed). added simulation (xswc_core.sv) which instanciates 7 ports and wrapped xswc_core)
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- 17 Jan, 2012 10 commits
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Maciej Lipinski authored
swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have a swcore which has pWB I/F, next step: change the simulation to test how it works
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Maciej Lipinski authored
swcore[v2->v3 port]: simulation working for altera ip/genrams but cannot make it work for xilinx, leaving simulation with xilinx for later
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
swcore[v2->v3 port] the old simulation works (depending on some old code, e.g.: platform/genrams) that is not commited..
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Maciej Lipinski authored
swcore[v2->v3 port]: changed generic_ssram_dualport_singleclock to generic_dpram in packet_mem and linked_list
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 12 Jan, 2012 3 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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